10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Chapter 14 Timing Diagrams

Address, AEN, nBE[3:0]

t2

Valid

nADS

 

t3

t4

Read Data

Valid

t6

t1t5

nRD, nWR t5A

Write Data

Valid

Figure 14.1 Asynchronous Cycle - nADS=0

 

PARAMETER

MIN

TYP

MAX

UNITS

 

 

 

 

 

 

t1

A1-A15, AEN, nBE[3:0] Valid to nRD, nWR Active

2

 

 

ns

 

 

 

 

 

 

t2

A1-A15, AEN, nBE[3:0] Hold After nRD, nWR Inactive (Assuming

5

 

 

ns

 

nADS Tied Low)

 

 

 

 

 

 

 

 

 

 

t3

nRD Low to Valid Data

 

 

15

ns

 

 

 

 

 

 

t4

nRD High to Data Invalid

2

 

15

ns

 

 

 

 

 

 

t5

Data Setup to nWR Inactive

10

 

 

ns

 

 

 

 

 

 

t5A

Data Hold After nWR Inactive

5

 

 

ns

 

 

 

 

 

 

t6

nRD Strobe Width

15

 

 

ns

 

 

 

 

 

 

Revision 1.91 (08-18-08)

110

SMSC LAN91C111 REV C

DATASHEET