10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

8.23Bank 3 - Management Interface

 

OFFSET

NAME

 

TYPE

SYMBOL

 

 

 

 

MANAGEMENT

 

 

 

 

 

 

8

 

INTERFACE

 

READ/WRITE

MGMT

 

 

 

 

 

 

 

 

 

 

 

 

HIGH

Reserved

MSK_

Reserved

 

Reserved

Reserved

 

Reserved

Reserved

Reserved

BYTE

 

CRS100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

 

1

0

 

0

1

1

 

 

 

 

 

 

 

 

 

 

 

LOW

 

Reserved

 

MDOE

 

MCLK

MDI

MDO

BYTE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

 

1

0

 

0

MDI Pin

0

 

 

 

 

 

 

 

 

 

 

 

MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode (SWFDUP=0). MDO - MII Management output. The value of this bit drives the MDO pin.

MDI - MII Management input. The value of the MDI pin is readable using this bit.

MDCLK - MII Management clock. The value of this bit drives the MDCLK pin.

MDOE - MII Management output enable. When high pin MDO is driven, when low pin MDO is tri- stated.

The purpose of this interface, along with the corresponding pins is to implement MII PHY management in software.

8.24Bank 3 - Revision Register

 

 

OFFSET

 

NAME

 

TYPE

 

SYMBOL

 

 

 

A

REVISION REGISTER

READ ONLY

 

REV

 

 

 

 

 

 

 

 

 

 

 

 

 

HIGH

 

 

 

 

 

 

 

 

 

 

 

 

BYTE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

1

1

0

 

0

 

1

1

 

 

 

 

 

 

 

 

 

 

 

 

 

LOW

 

 

 

CHIP

 

 

 

 

REV

 

BYTE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

0

1

0

 

0

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

CHIP - Chip ID. Can be used by software drivers to identify the device used.

REV - Revision ID. Incremented for each revision of a given device.

SMSC LAN91C111 REV C

67

Revision 1.91 (08-18-08)

DATASHEET