10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

TX Interrupt With AUTO_RELEASE = FALSE

1. Save the Packet Number Register

Saved_PNR = Read Byte (Bank 2, Offset 2)

2. Read the EPH Status Register

Temp = Read (Bank 0, Offset 2)

3. Acknowledge TX Interrupt

Write Byte (0x02, (Bank 2, Offset C));

4.Check for Status of Transmission If ( Temp AND 0x0001)

{

//If Successful Transmission

Step 4.1.1: Issue MMU Release (Release Specific Packet) Write (0x00A0, (Bank2, Offset 0));

Step 4.1.2: Return from the routine

}

else

{

//Transmission has FAILED

// Now we can either release or re-enqueue the packet

Step 4.2.1: Get the packet to release/re-enqueue, stored in FIFO Temp = Read (Bank 2, Offset 4)

Temp = Temp & 0x003F

Step 4.2.2: Write to the PNR

Write (Temp, (Bank2, Offset 2))

Step 4.2.3

// Option 1: Release the packet

Write (0x00A0, (Bank2, Offset 0)); //Option 2: Re-Enqueue the packet

Write (0x00C0, (Bank2, Offset 0));

Step 4.2.4: Re-Enable Transmission

Temp = Read(Bank0, Offset 0);

Temp = Temp2 OR 0x0001

Write (Temp2, (Bank 0, Offset 0));

Step 4.2.5: Return from the routine

}

5. Restore the Packet Number Register

Write Byte (Saved_PNR, (Bank 2, Offset 2))

Figure 10.3 TX INTR

Revision 1.91 (08-18-08)

90

SMSC LAN91C111 REV C

DATASHEET