SMSC LAN91C111 8-32bit, Bus, PHY, Unit, DMA

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

EEPROM	MII
INTERFACE

Control

Address

Data

			Control
		Control			Control
	Control	Arbiter				Control
8-32 bit						TPO
Bus					Ethernet	10/100
Interface
	Control	MMU			Protocol	PHY
Unit			TX/RX	DMA
					Handler
			FIFO
			Pointer		(EPH)
	WR				TX Data	TXD[0-3]
			32-bit Data
	FIFO	8K Byte				TPI
		Dynamically
		Allocated				RXD[0-3]
	RD	SRAM	32-bit Data		RX Data
	FIFO

Figure 3.2 Block Diagram

The diagram shown in Figure 3.2 describes the supported Host interfaces, which include ISA or Generic Embedded. The Host interface is an 8, 16 or 32 bit wide address / data bus with extensions for 32, 16 and 8 bit embedded RISC and ARM processors.

The figure shown next page describes the SMSC LAN91C111 functional blocks required to integrate a 10/100 Ethernet Physical layer framer to the internal MAC.

Revision 1.91 (08-18-08) 12 SMSC LAN91C111 REV C

DATASHEET