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Datasheet
7.4BIU Block
The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are used for each one. Transparent latches are added on the address path using rising nADS for latching.
When working with an asynchronous bus like ISA, the read and write operations are controlled by the edges of nRD and nWR. ARDY is used for notifying the system that it should extend the access cycle. The leading edge of ARDY is generated by the leading edge of nRD or nWR while the trailing edge of ARDY is controlled by the internal LAN91C111 clock and, therefore, asynchronous to the bus.
In the synchronous VL Bus type mode, nCYCLE and LCLK are used to for read and write operations. Completion of the cycle may be determined by using nSRDY. nSRDY is controlled by LCLK and synchronous to the bus.
Direct 32 bit access to the Data Path is supported by using the nDATACS input. By asserting nDATACS, external DMA type of devices will bypass the BIU address decoders and can sequentially access memory with no CPU intervention. nDATACS accesses can be used in the EISA DMA burst mode (nVLBUS=1) or in asynchronous cycles. These cycles MUST be 32 bit cycles. Please refer to the corresponding timing diagrams for details on these cycles.
The BIU is implemented using the following principles:
a.Address decoding is based on the values of
b.Address latching is performed by using transparent latches that are transparent when nADS=0 and nRD=1, nWR=1 and latch on nADS rising edge.
c.Byte, word and doubleword accesses to all registers and Data Path are supported except a doubleword write to offset Ch will only write the BANK SELECT REGISTER (offset 0x0Fh).
d.No bus byte swapping is implemented (no eight bit mode).
e.Word swapping as a function of A1 is implemented for 16 bit bus support.
f.The asynchronous interface uses nRD and nWR strobes. If necessary, ARDY is negated on the leading edge of the strobe. The ARDY trailing edge is controlled by CLK.
g.The VLBUS synchronous interface uses LCLK, nADS, and W/nR as defined in the VESA specification as well as nCYCLE to control read and write operations and generate nSRDY.
h.EISA burst DMA cycles to and from the DATA REGISTER are supported as defined in the EISA Slave Mode "C" specification when nDATACS is driven by nDAK.
i.Synchronous and asynchronous cycles can be mixed as long as they are not active simultaneously.
j.Address and bank selection can be bypassed to generate 32 bit Data Path accesses by activating the nDATACS pin.
7.5MAC-PHY Interface
The LAN91C111 integrates the IEEE 802.3 Physical Layer (PHY) and Media Access Control (MAC) into the same silicon. The data path connection between the MAC and the internal PHY is provided by the internal MII. The LAN91C111 also supports the EXT_PHY mode for the use of an external PHY, such as HPNA. This mode isolates the internal PHY to allow interface with an external PHY through the MII pins. To enter this mode, set EXT PHY bit to 1 in the Configuration Register.
7.5.1Management Data Software Implementation
The MII interface contains of a pair of signals that physically transport the management information across the MII, a frame format and a protocol specification for exchanging management frames, and a register set that can be read and written using these frames. MII management refers to the ability of a management entity to communicate with PHY via the MII serial management interface (MI) for the purpose of displaying, selecting and/or controlling different PHY options. The host manipulates the MAC to drive the MII management serial interface. By manipulating the MAC's registers, MII management frames are generated on the management interface for reading or writing information from the PHY registers. Timing and framing for each management command is to be generated by the CPU (host).
SMSC LAN91C111 REV C | 21 | Revision 1.91 |
DATASHEET