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Datasheet
Table 12.3 EISA 32 Bit Slave Signal Connections (continued)EISA BUS |
| LAN91C111 | NOTES |
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SIGNAL |
| SIGNAL |
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Latched |
| nRD | I/O Read strobe - asynchronous read accesses. Address is valid | ||||||||
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| before its leading edge. Must not be active during DMA bursts if | ||||||||
nCMD |
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| DMA is supported. |
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Latched |
| nWR | I/O Write strobe - asynchronous write access. Address is valid | ||||||||
combined with |
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| before leading edge . Data latched on trailing edge. Must not be | ||||||||
nCMD |
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| active during DMA bursts if DMA is supported. | ||||||||
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nSTART |
| nADS | Address strobe is connected to EISA nSTART. | ||||||||
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RESDRV |
| RESET |
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nBE0 nBE1 nBE2 |
| nBE0 n BE1 nBE2 | Byte enables. Latched on nADS rising edge. | ||||||||
nBE3 |
| nBE3 |
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IRQn |
| INTR0 | Interrupts used as active high edge triggered | ||||||||
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| 32 bit data bus. The bus byte(s) used to access the device are a | ||||||||||
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| function of |
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| nBE0 | nBE1 | nBE2 |
| nBE3 |
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| 0 | 0 | 0 |
| 0 |
| Double word access |
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| 0 | 0 | 1 |
| 1 |
| Low word access |
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| 1 | 1 | 0 |
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| High word access |
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| 0 | 1 | 1 |
| 1 |
| Byte 0 access |
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| 1 | 0 | 1 |
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| Byte 1 access |
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| 1 | 1 | 0 |
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| Byte 2 access |
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| 1 | 1 | 1 |
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| Byte 3 access |
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| Not used = | ||||||||
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| nBE3 override the value of A1, which is tied low in this application. | ||||||||
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| Other combinations of nBE are not supported by the LAN91C111. | ||||||||
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| Software drivers are not anticipated to generate them. | ||||||||
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nEX32 |
| nLDEV | nLDEV is a totem pole output. nLDEV is active on valid decodes of | ||||||||
nNOWS |
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| LAN91C111 pins | ||||||||
(optional additional |
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| except that it should go inactive on nSTART rising. nNOWS can be | ||||||||
logic) |
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| used to request compressed cycles (1.5 BCLK long, nRD/nWR will | ||||||||
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| be 1/2 BCLK wide). |
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THE FOLLOWING SIGNALS SUPPORT SLAVE DMA TYPE "C" BURST CYCLES | |||||||||||
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BCLK |
| LCLK | EISA Bus Clock. Data transfer clock for DMA bursts. | ||||||||
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nDAK<n> |
| nDATACS | DMA Acknowledge. Active during Slave DMA cycles. Used by the | ||||||||
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| LAN91C111 as nDATACS direct access to data path. | ||||||||
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nIORC |
| W/nR | Indicates the direction and timing of the DMA cycles. High during | ||||||||
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| LAN91C111 writes, low during LAN91C111 reads. | ||||||||
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nIOWC |
| nCYCLE | Indicates slave DMA writes. |
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nEXRDY |
| nRDYRTN | EISA bus signal indicating whether a slave DMA cycle will take place | ||||||||
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| on the next BCLK rising edge, or should be postponed. nRDYRTN | ||||||||
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| is used as an input in the slave DMA mode to bring in EXRDY. | ||||||||
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UNUSED PINS |
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VCC |
| nVLBUS |
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SMSC LAN91C111 REV C |
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| 103 |
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| Revision 1.91 | ||
DATASHEET