10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Chapter 12 Application Considerations

The LAN91C111 is envisioned to fit a few different bus types. This section describes the basic guidelines, system level implications and sample configurations for the most relevant bus types. All applications are based on buffered architectures with a private SRAM bus.

FAST ETHERNET SLAVE ADAPTER

Slave non-intelligent board implementing 100 Mbps and 10 Mbps speeds.

Adapter requires:

1.LAN91C111 chip

2.Serial EEPROM (93C46)

3.Some bus specific glue logic

Target systems:

1.VL Local Bus 32 bit systems

2.High-end ISA or non-burst EISA machines

3.EISA 32 bit slave

VL Local Bus 32 Bit Systems

On VL Local Bus and other 32 bit embedded systems the LAN91C111 is accessed as a 32 bit peripheral in terms of the bus interface. All registers except the DATA REGISTER will be accessed using byte or word instructions. Accesses to the DATA REGISTER could use byte, word, or dword instructions.

 

Table 12.1 VL Local Bus Signal Connections

 

 

 

 

 

VL BUSLAN91C111NOTES

 

SIGNAL

SIGNAL

 

 

 

 

 

 

A2-A15

A2-A15

Address bus used for I/O space and register decoding, latched by nADS

 

 

rising edge, and transparent on nADS low time.

 

 

 

 

M/nIO

AEN

Qualifies valid I/O decoding - enabled access when low. This signal is

 

 

latched by nADS rising edge and transparent on nADS low time.

 

 

 

W/nR

W/nR

Direction of access. Sampled by the LAN91C111 on first rising clock that

 

 

has nCYCLE active. High on writes, low on reads.

 

 

 

 

nRDYRTN

nRDYRTN

Ready return. Direct connection to VL bus.

 

 

 

 

nLRDY

nSRDY and some

nSRDY has the appropriate functionality and timing to create the VL

 

logic

nLRDY except that nLRDY behaves like an open drain output most of

 

 

the time.

 

 

 

 

LCLK

LCLK

Local Bus Clock. Rising edges used for synchronous bus interface

 

 

transactions.

 

 

 

 

 

nRESET

RESET

Connected via inverter to the LAN91C111.

 

 

 

 

nBE0 nBE1

nBE0 nBE1 nBE2

Byte enables. Latched transparently by nADS rising edge.

nBE2 nBE3

nBE3

 

 

 

 

 

nADS

nADS, nCYCLE

Address Strobe is connected directly to the VL bus. nCYCLE is created

 

 

typically by using nADS delayed by one LCLK.

 

 

 

 

IRQn

INTR0

Typically uses the interrupt lines on the ISA edge connector of VL bus

 

 

 

 

Revision 1.91 (08-18-08)

98

SMSC LAN91C111 REV C

DATASHEET