10/100 Non-PCI Ethernet Single Chip MAC + PHY

 

 

Datasheet

 

 

 

 

S/W DRIVER

MAC SIDE

 

 

 

6

 

Upon transmit completion the first word in memory is

 

 

written with the status word. The packet number is

 

 

moved from the TX FIFO into the TX completion

 

 

FIFO. Interrupt is generated by the TX completion

 

 

FIFO being not empty.

 

 

If a TX failure occurs on any packets, TX INT is

 

 

generated and TXENA is cleared, transmission

 

 

sequence stops. The packet number of the failure

 

 

packet is presented at the TX FIFO PORTS Register.

 

 

 

7

SERVICE INTERRUPT - Read Interrupt Status

 

 

Register. If it is a transmit interrupt, read the TX FIFO

 

 

Packet Number from the FIFO Ports Register. Write

 

 

the packet number into the Packet Number Register.

 

 

The corresponding status word is now readable from

 

 

memory. If status word shows successful

 

 

transmission, issue RELEASE packet number

 

 

command to free up the memory used by this packet.

 

 

Remove packet number from completion FIFO by

 

 

writing TX INT Acknowledge Register.

 

 

Option 1) Release the packet.

 

 

Option 2) Check the transmit status in the EPH

 

 

STATUS Register, write the packet number of the

 

 

current packet to the Packet Number Register, re-

 

 

enable TXENA, then go to step 4 to start the TX

 

 

sequence again.

 

 

 

 

10.3Typical Flow of Events for Transmit (Auto Release = 1)

 

S/W DRIVER

MAC SIDE

 

 

 

1

ISSUE ALLOCATE MEMORY FOR TX - N BYTES -

 

 

the MMU attempts to allocate N bytes of RAM.

 

 

 

 

2

WAIT FOR SUCCESSFUL COMPLETION CODE -

 

 

Poll until the ALLOC INT bit is set or enable its mask

 

 

bit and wait for the interrupt. The TX packet number

 

 

is now at the Allocation Result Register.

 

 

 

 

3

LOAD TRANSMIT DATA - Copy the TX packet

 

 

number into the Packet Number Register. Write the

 

 

Pointer Register, then use a block move operation

 

 

from the upper layer transmit queue into the Data

 

 

Register.

 

 

 

 

4

ISSUE "ENQUEUE PACKET NUMBER TO TX FIFO"

 

 

- This command writes the number present in the

 

 

Packet Number Register into the TX FIFO. The

 

 

transmission is now enqueued. No further CPU

 

 

intervention is needed until a transmit interrupt is

 

 

generated.

 

 

 

 

5

 

The enqueued packet will be transferred to the MAC

 

 

block as a function of TXENA (nTCR) bit and of the

 

 

deferral process (1/2 duplex mode only) state.

 

 

 

6

 

Transmit pages are released by transmit completion.

 

 

 

Revision 1.91 (08-18-08)

86

SMSC LAN91C111 REV C

DATASHEET