10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

PIN NO.

 

NAME

SYMBOL

BUFFER

DESCRIPTION

 

 

TQFP

QFP

TYPE

 

 

 

 

 

 

 

 

 

 

 

 

 

9

11

EEPROM Clock

EESK

O4

Output. 4 μsec clock used to shift data in

 

 

 

 

 

and out of the serial EEPROM.

 

 

 

 

 

 

10

12

EEPROM

EECS

O4

Output. Serial EEPROM chip select.

 

 

Select

 

 

Used for selection and command framing

 

 

 

 

 

of the serial EEPROM.

 

 

 

 

 

 

7

9

EEPROM Data

EEDO

O4

Output. Connected to the DI input of the

 

 

Out

 

 

serial EEPROM.

 

 

 

 

 

 

8

10

EEPROM Data

EEDI

I with

Input. Connected to the DO output of the

 

 

In

 

pulldown **

serial EEPROM.

 

 

 

 

 

 

3-5

5-7

I/O Base

IOS0-IOS2

I with

Input. External switches can be

 

 

 

 

pullup**

connected to these lines to select

 

 

 

 

 

between predefined EEPROM

 

 

 

 

 

configurations.

 

 

 

 

 

 

6

8

Enable

ENEEP

I with

Input. Enables (when high or open)

 

 

EEPROM

 

pullup**

LAN91C111 accesses to the serial

 

 

 

 

 

EEPROM. Must be grounded if no

 

 

 

 

 

EEPROM is connected to the

 

 

 

 

 

LAN91C111.

 

 

 

 

 

 

127, 128

1, 2

Crystal 1

XTAL1

Iclk**

An external 25 MHz crystal is connected

 

 

Crystal 2

XTAL2

 

across these pins. If a TTL clock is

 

 

 

 

 

supplied instead, it should be connected

 

 

 

 

 

to XTAL1 and XTAL2 should be left open.

 

 

 

 

 

XTAL1 is the 5V tolerant input of the

 

 

 

 

 

internal amplifier and XTAL2 is the output

 

 

 

 

 

of the internal amplifier.

 

 

 

 

 

 

1, 33, 44,

3, 35, 46,

Power

VDD

 

+3.3V Power supply pins.

62, 77, 98,

64, 79,

 

 

 

 

110, 120

100, 112,

 

 

 

 

 

122

 

 

 

 

 

 

 

 

 

 

11, 16

13, 18

Analog Power

AVDD

 

+3.3V Analog power supply pins.

 

 

 

 

 

 

24, 39, 52,

26, 41, 54,

Ground

GND

 

Ground pins.

57, 67, 72,

59, 69, 74,

 

 

 

 

93, 103,

95, 105,

 

 

 

 

108, 117

110, 119

 

 

 

 

 

 

 

 

 

 

13, 19

15, 21

Analog Ground

AGND

 

Analog Ground pins

 

 

 

 

 

 

21

23

Loopback

LBK

O4

Output. Active when LOOP bit is set

 

 

 

 

 

(TCR bit 1).

 

 

 

 

 

 

20

22

nLink Status

nLNK

I with

Input. General-purpose input port used to

 

 

 

 

pullup

convey LINK status (EPHSR bit 14).

 

 

 

 

 

 

28

30

nCNTRL

nCNTRL

O12

General Purpose Control Pin

 

 

 

 

 

 

47

49

X25out

X25out

O12

25Mhz Output to external PHY

 

 

 

 

 

 

111

113

Transmit Enable

TXEN100

O12

Output to MII PHY. Envelope to 100

 

 

100 Mbps

 

 

Mbps transmission.

 

 

 

 

 

 

119

121

Carrier Sense

CRS100

I with

Input from MII PHY. Envelope of packet

 

 

100 Mbps

 

pulldown

reception used for deferral and backoff

 

 

 

 

 

purposes.

 

 

 

 

 

 

SMSC LAN91C111 REV C

 

17

 

Revision 1.91 (08-18-08)

DATASHEET