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Datasheet
OFFSET | NAME | TYPE | SYMBOL |
| INTERRUPT |
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| ACKNOWLEDGE |
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C | REGISTER | WRITE ONLY | IST |
MDINT | Reserved |
| RX_OVRN |
| TX EMPTY | TX INT |
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| INT |
| INT |
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| OFFSET |
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| NAME | TYPE | SYMBOL |
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| INTERRUPT MASK |
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| D |
| REGISTER | READ/WRITE |
| MSK |
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MDINT | Reserved |
| EPH INT |
| RX_OVRN | ALLOC INT | TX EMPTY | TX INT | RCV INT | |
MASK |
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| MASK |
| INT | MASK | INT |
| MASK | MASK |
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| MASK |
| MASK |
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0 | 0 |
| 0 |
| 0 | 0 | 0 |
| 0 | 0 |
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This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A MASK bit being set will cause a hardware interrupt.
MDINT - Set when the following bits in the PHY MI Register 18 (Serial Port Status Output Register) change state.
1. LNKFAIL, 2) LOSSSYNC, 3) CWRD, 4) SSD, 5) ESD, 6) PROL, 7) JAB, 8) SPDDET, 9) DPLXDET.
These bits automatically latch upon changing state and stay latched until they are read. When they are read, the bits that caused the interrupt to happen are updated to their current value. The MDINT bit will be cleared by writing the acknowledge register with MDINT bit set.
Reserved - Must be 0
EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special conditions. This bit merges exception type of interrupt sources, whose service time is not critical to the execution speed of the low level drivers. The exact nature of the interrupt can be obtained from the EPH Status Register (EPHSR), and enabling of these sources can be done via the Control Register. The possible sources are:
LINK - Link Test transition
CTR_ROL - Statistics counter roll over
TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and the specific reason will be reflected by the bits:
| SQET - SQE Error |
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| LOST CARR - Lost Carrier |
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SMSC LAN91C111 REV C | 63 | Revision 1.91 | |
DATASHEET