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Datasheet
Register) and determine the duplex mode. When this bit is set (1), the Internal PHY will operate at full duplex mode. When this bit is cleared (0), the Internal PHY will operate at half Duplex mode. When the ANEG bit = 1, this bit is ignored and duplex mode is determined by the outcome of the Auto- negotiation or this bit is overridden by the DPLX bit in the PHY Register 0 (Control Register) when the ANEG_EN bit in the PHY Register 0 (Control Register) is clear.
ANEG –
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| DUPLEX |
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| MODE |
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| AUTO- |
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| CONTROL |
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| WANT TO DO? | CONTROL BITS |
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| Try to | ANEG |
| ANEG_E |
| TX_FDX |
| TX_HDX |
| 10_FDX |
| 10_HDX |
| SWFDUP |
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| Control |
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| 100 Full Duplex | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
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| 100 Half Duplex | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
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| 10 Full Duplex | 1 | 1 | 0 | 0 | 1 | 1 | 1 |
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| 10 Half Duplex | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
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| DUPLEX |
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| MODE |
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| SPEED AND DUPLEX MODE CONTROL |
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| CONTROL BITS |
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| Try to Manually Set to |
| ANEG |
| ANEG_E |
| SPEED |
| DPLX |
| SPEED |
| DPLX |
| SWFDUP |
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| Register 0 |
| RPCR |
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| Transmit |
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| (PHY) |
| (MAC |
| (MAC |
| 0 |
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| Control |
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| Offset A) |
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| 100 Full Duplex |
| 0 |
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| 1 |
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| X |
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| 100 Half Duplex |
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| Revision 1.91 |
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| 52 |
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| SMSC LAN91C111 REV C |
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DATASHEET