SMSC LAN91C111 ISA BUS, NOTES, SIGNAL, SIGNAL, EISA BUS, LAN91C111, EISA 32 BIT SLAVE, Figure 12.2 LAN91C111 on ISA BUS, Table 12.3 EISA 32 Bit Slave Signal Connections

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

ISA BUS

A1-A15, AEN	A1-A15, AEN
RESET	RESET
VCC	nBE2, nBE3
D0-D15	D0-D15
IRQ	INTR0	LAN91C111

nIORDnRD

nIOWRnWR

A0nBE0

nSBHEnBE1

nLDEV

nIOCS16O.C.

Figure 12.2 LAN91C111 on ISA BUSEISA 32 BIT SLAVE

On EISA the LAN91C111 is accessed as a 32 bit I/O slave, along with a Slave DMA type "C" data path option. As an I/O slave, the LAN91C111 uses asynchronous accesses. In creating nRD and nWR inputs, the timing information is externally derived from nCMD edges. Given that the access will be at least 1.5 to 2 clocks (more than 180ns at least) there is no need to negate EXRDY, simplifying the EISA interface implementation. As a DMA Slave, the LAN91C111 accepts burst transfers and is able to sustain the peak rate of one doubleword every BCLK. Doubleword alignment is assumed for DMA transfers. The LAN91C111 will sample EXRDY and postpone DMA cycles if the memory cycle solicits wait states.

	Table 12.3 EISA 32 Bit Slave Signal Connections
EISA BUS	LAN91C111	NOTES
SIGNAL	SIGNAL
LA2-LA15	A2-A15	Address bus used for I/O space and register decoding, latched by
		nADS (nSTART) trailing edge.
M/nIO	AEN	Qualifies valid I/O decoding - enabled access when low. These
AEN		signals are externally ORed. Internally the AEN pin is latched by
		nADS rising edge and transparent while nADS is low.
Revision 1.91 (08-18-08)		102	SMSC LAN91C111 REV C

DATASHEET