10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Reserved – Must be 0.

8.11Bank 1 - Configuration Register

OFFSET

NAME

TYPE

SYMBOL

 

CONFIGURATION

 

 

0

REGISTER

READ/WRITE

CR

The Configuration Register holds bits that define the adapter configuration and are not expected to change during run-time. This register is part of the EEPROM saved setup.

HIGH

EPH

Reserved

Reserved

NO

Reserved

GPCNTRL

EXT PHY

Reserved

BYTE

Power

 

 

WAIT

 

 

 

 

 

EN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

0

0

0

0

0

 

 

 

 

 

 

 

 

 

LOW

Reserved

Reserved

 

Reserved

 

Reserved

Reserved

Reserved

BYTE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

1

0

0

0

1

 

 

 

 

 

 

 

 

 

EPH Power EN - Used to selectively power transition the EPH to a low power mode. When this bit is cleared (0), the Host will place the EPH into a low power mode. The Ethernet MAC will gate the 25Mhz TX and RX clock so that the Ethernet MAC will no longer be able to receive and transmit packets. The Host interface however, will still be active allowing the Host access to the device through Standard IO access. All LAN91C111 registers will still be accessible. However, status and control will not be allowed until the EPH Power EN bit is set AND a RESET MMU command is initiated.

NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if not ready for a transfer. When clear, negates ARDY for two to three clocks on any cycle to the LAN91C111.

GPCNTRL - This bit is a general purpose output port. Its inverse value drives pin nCNTRL and it is typically connected to a SELECT pin of the external PHY device such as a power enable. It can be used to select the signaling mode for the external PHY or as a general purpose non-volatile configuration pin. Defaults low.

EXT PHY – External PHY Enabled.

This bit, when set (1):

a.Enables the external MII.

b.The Internal PHY is disabled and is disconnected (Tri-stated from the internal MII along with any sideband signals (such as MDINT) going to the MAC Core).

When this bit is cleared (0 - Default):

a.The internal PHY is enabled.

b.The external MII pins, including the MII Management interface pins are tri-stated. Reserved – Reserved bits.

Revision 1.91 (08-18-08)

54

SMSC LAN91C111 REV C

DATASHEET