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SMSC LAN91C111 manual 5

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10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Chapter 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Chapter 16 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

SMSC LAN91C111 REV C

5

Revision 1.91 (08-18-08)

DATASHEET

Contents
LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY Network Interface ORDER NUMBERS: Table of Contents Chapter Page Page List of Figures List of Tables Chapter 1 General Description Chapter 2 Pin Configurations LAN91C111 FEAST Pin Configuration LAN91C111 FEASTTM 128 PIN QFP Figure 2.2 Pin Configuration - LAN91C111-FEAST128 PIN QFP Chapter 3 Block Diagrams Host System 8-32bit Bus PHY Unit DMA CSMA/CD Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram Chapter 4 Signal Descriptions Chapter 5 Description of Pin Functions Page Page Note Chapter 6 Signal Description Parameters Buffer Types Chapter 7 Functional Description 7.1Clock Generator Block 7.2CSMA/CD Block 7.3MMU Block 7.4BIU Block 7.5MAC-PHYInterface 7.5.2Management Data Timing 7.5.3MI Serial Port Frame Structure Page 7.5.4MII Packet Data Communication with External PHY Figure 7.2 MII Frame Format & MII Nibble Order 7.6Serial EEPROM Interface 7.7Internal Physical Layer Figure 7.3 TX/10BT Frame Format 7.7.1MII Disable 7.7.2Encoder 4B5B Encoder - 100 Mbps Manchester Encoder - 10 Mbps 7.7.3Decoder Page 7.7.4Clock and Data Recovery Clock Recovery - 100 Mbps Data Recovery - 100 Mbps Clock Recovery - 10 Mbps Data Recovery - 10 Mbps 7.7.7Twisted Pair Transmitter Transmitter - 100 Mbps Transmitter - 10 Mbps Page Page 7.7.8Twisted Pair Receiver Receiver - 100 Mbps Receiver - 10 Mbps Page 7.7.9Collision Collision Test 7.7.10Start of Packet 7.7.11End of Packet 7.7.12Link Integrity & AutoNegotiation General 10BASE-TLink Integrity Algorithm - 10Mbps Page Page 7.7.13Jabber Jabber Disable 7.7.14Receive Polarity Correction Note: 7.7.15Full Duplex Mode 100/10 Mbps SELECTION 7.7.16Loopback Diagnostic Loopback 7.7.17PHY Powerdown 7.8Reset Chapter 8 MAC Data Structures and Registers 8.1Frame Format In Buffer Memory 8.2Receive Frame Status 8.3I/O Space 8.4Bank Select Register 8.5Bank 0 - Transmit Control Register 8.6Bank 0 - EPH Status Register 8.7Bank 0 - Receive Control Register 8.8Bank 0 - Counter Register 8.9Bank 0 - Memory Information Register 8.10Bank 0 - Receive/Phy Control Register DUPLEX MODE AUTO CONTROL WHAT DO YOU LS2A LS1A LS0A LED SELECT SIGNAL – LEDA LS2B 8.11Bank 1 - Configuration Register 8.12Bank 1 - Base Address Register 8.13Bank 1 - Individual Address Registers 8.14Bank 1 - General Purpose Register 8.15Bank 1 - Control Register 8.16Bank 2 - MMU Command Register 8.17Bank 2 - Packet Number Register 8.18Bank 2 - FIFO Ports Register 8.19Bank 2 - Pointer Register 8.20Bank 2 - Data Register 8.21Bank 2 - Interrupt Status Registers INTERRUPT ACKNOWLEDGE INTERRUPT MASK MSK Page Structure Interrupt 2.8 Figure 8.22Bank 3 - Multicast Table Registers 8.23Bank 3 - Management Interface 8.24Bank 3 - Revision Register 8.25 Bank 3 - RCV Register 8.26Bank 7 - External Registers CYCLE NCSOUT LAN91C111 DATA BUS Chapter 9 PHY MII Registers Table 9.1 MII Serial Frame Structure DEFINITION Page Register Port Serial MII 2.9 Table MAP 9.1Register 0. Control Register 9.2Register 1. Status Register 9.3Register 2&3. PHY Identifier Register 9.4Register 4. Auto-NegotiationAdvertisement Register 9.5Register 5. Auto-NegotiationRemote End Capability Register 9.6Register 16. Configuration 1- Structure and Bit Definition 9.7Register 17. Configuration 2 - Structure and Bit Definition 9.8Register 18. Status Output - Structure and Bit Definition 9.9Register 19. Mask - Structure and Bit Definition 9.10Register 20. Reserved - Structure and Bit Definition Page Chapter 10 Software Driver and Hardware Sequence Flow 10.1Software Driver and Hardware Sequence Flow for Power Management 10.2Typical Flow of Events for Transmit (Auto Release = 0) 10.3Typical Flow of Events for Transmit (Auto Release = 1) 10.4Typical Flow of Event For Receive Figure 10.1 Interrupt Service Routine Figure 10.2 RX INTR TX Interrupt With AUTO_RELEASE = FALSE Byte Figure 10.4 TXEMPTY INTR (Assumes Auto Release Option Selected) Figure 10.5 Drive Send and Allocate Routines MEMORY PARTITIONING INTERRUPT GENERATION Figure 10.6 Interrupt Generation for Transmit, Receive, MMU Chapter 11 Board Setup Information Page IOS2-0 WORD ADDRESS Chapter 12 Application Considerations Table 12.1 VL Local Bus Signal Connections (continued) UNUSED PINS VLBUS RESETLAN91C111 Table 12.2 High-EndISA or Non-BurstEISA Machines Signal Connectors (continued) ISA BUS Table 12.3 EISA 32 Bit Slave Signal Connections (continued) EISA BUS Chapter 13 Operational Description 13.1Maximum Guaranteed Ratings 13.2DC Electrical Characteristics Page CAPACITANCE TA = 25°C; fc = 1MHz; VCC LIMITS UNIT TEST CONDITION CAPACITIVE LOAD ON OUTPUTS 13.3Twisted Pair Characteristics, Transmit 13.4Twisted Pair Characteristics, Receive Chapter 14 Timing Diagrams Figure 14.2 Asynchronous Cycle - Using nADS Figure 14.3 Asynchronous Cycle - nADS=0 Figure 14.4 Asynchronous Ready Figure 14.5 Burst Write Cycles - nVLBUS=1 Figure 14.6 Burst Read Cycles - nVLBUS=1 Figure 14.7 Address Latching for All Modes Figure 14.8 Synchronous Write Cycle - nVLBUS=0 Figure 14.9 Synchronous Read Cycle - nVLBUS=0 Figure 14.10 MII Timing Table 14.1 Transmit Timing Characteristics Figure 14.11 Transmit Timing Table Receive Timing Characteristics Figure 14.12 Receive Timing, End of Packet - 10 MBPS Table 14.3 Collision and Jam Timing Characteristics Figure 14.13 Collision Timing, Receive Figure 14.14 Collision Timing, Transmit Figure 14.15 Jam Timing Table 14.4 Link Pulse Timing Characteristics a.) Transmit NLP b.) Receive NLP a.) Transmit FLP and Transmit FLP Burst b.) Receive FLP c.) Receive FLP Burst Figure 14.17 FLP Link Pulse Timing Chapter 15 Package Outlines Figure 15.2 128 Pin QFP Package Outline, 3.9 MM Footprint Table 15.2 128 Pin QFP Package Parameters REMARKS Chapter 16 Revision History