10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

INTERFRAME

GAP

IDLE

 

 

 

 

 

ETHERNET MAC

 

 

 

 

 

 

INTERFRAME

 

 

 

 

 

 

FRAME

 

 

 

 

 

 

 

 

PREAMBLE

 

SFD

DA

 

SA

 

LN

 

 

LLC DATA

 

FCS

 

GAP

 

 

 

 

 

 

 

100 BASE-TX DATA SYMBOLS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSD

PREAMBLE

 

SFD

DA

 

SA

LN

 

 

LLC DATA

 

FCS

ESD

IDLE

 

 

 

 

 

 

 

 

 

IDLE

=

[ 1 1 1

1...]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSD

= [ 1 1 0 0 0 1 0 0 0 1]

 

 

 

BEFORE / AFTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PREAMBLE

= [ 1 0 1 0 ...] 62 BITS LONG

 

 

 

 

 

 

 

 

 

 

 

4B5B ENCODING,

 

 

 

 

 

 

 

 

 

 

SFD

= [ 1 1]

 

 

 

 

 

 

 

SCRAMBLING,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DA, SA, LN, LLC DATA, FCS

= [ DATA]

 

 

 

 

 

 

 

 

AND MLT3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ESD

= [ 0 1 1 0 1 0 0 1 1 1]

 

 

 

 

CODING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10 BASE-T DATA SYMBOLS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDLE

 

PREAMBLE

SFD

DA

SA

LN

 

LLC DATA

FCS

SOI

IDLE

 

 

 

 

IDLE

= [ NO TRANSITIONS]

 

 

 

 

 

 

 

 

 

 

 

PREAMBLE

= [ 1 0 1 0 ... ] 62 BITS LONG

 

 

BEFORE / AFTER

 

 

 

SFD

= [ 1 1]

 

 

 

 

 

 

 

 

DA, SA, LN, LLC DATA, FCS

= [ DATA]

 

 

 

 

 

 

MANCHESTER

 

 

 

 

 

 

 

 

ENCODING

 

 

 

 

 

 

 

 

 

 

 

 

SOI = [ 1 1 ] WITH NO MID BIT TRANSITION

Figure 7.3 TX/10BT Frame Format

On the transmit side for 100Mbps TX operation, data is received on the controller and then sent to the 4B5B encoder for formatting. The encoded data is then sent to the scrambler. The scrambled and encoded data is then sent to the TP transmitter. The TP transmitter converts the encoded and scrambled data into MLT-3 ternary format, reshapes the output, and drives the twisted pair cable.

On the receive side for 100Mbps TX operation, the twisted pair receiver receives incoming encoded and scrambled MLT-3 data from the twisted pair cable, remove any high frequency noise, equalizes the input signal to compensate for the effects of the cable, qualifies the data with a squelch algorithm, and converts the data from MLT-3 coded twisted pair levels to internal digital levels. The output of the twisted pair receiver then goes to a clock and data recovery block which recovers a clock from the incoming data, uses the clock to latch in valid data into the device, and converts the data back to NRZ format. The NRZ data is then unscrambled and decoded by the 4B5B decoder and descrambler, respectively, and outputted to the Ethernet controller.

Revision 1.91 (08-18-08)

26

SMSC LAN91C111 REV C

DATASHEET