10/100 Non-PCI Ethernet Single Chip MAC + PHY

 

Datasheet

 

 

 

 

 

S/W DRIVER

MAC SIDE

 

 

 

7

 

The MAC generates a TXEMPTY interrupt upon a

 

 

completion of a sequence of enqueued packets.

 

 

If a TX failure occurs on any packets, TX INT is

 

 

generated and TXENA is cleared, transmission

 

 

sequence stops. The packet number of the failure

 

 

packet is presented at the TX FIFO PORTS Register.

 

 

 

8

SERVICE INTERRUPT – Read Interrupt Status

 

 

Register, exit the interrupt service routine.

 

 

Option 1) Release the packet.

 

 

Option 2) Check the transmit status in the EPH

 

 

STATUS Register, write the packet number of the

 

 

current packet to the Packet Number Register, re-

 

 

enable TXENA, then go to step 4 to start the TX

 

 

sequence again.

 

 

 

 

10.4Typical Flow of Event For Receive

 

S/W DRIVER

MAC SIDE

 

 

 

1

ENABLE RECEPTION - By setting the RXEN bit.

 

 

 

 

2

 

A packet is received with matching address. Memory

 

 

is requested from MMU. A packet number is

 

 

assigned to it. Additional memory is requested if

 

 

more pages are needed.

 

 

 

3

 

The internal DMA logic generates sequential

 

 

addresses and writes the receive words into memory.

 

 

The MMU does the sequential to physical address

 

 

translation. If overrun, packet is dropped and

 

 

memory is released.

 

 

 

4

 

When the end of packet is detected, the status word

 

 

is placed at the beginning of the receive packet in

 

 

memory. Byte count is placed at the second word. If

 

 

the CRC checks correctly the packet number is

 

 

written into the RX FIFO. The RX FIFO, being not

 

 

empty, causes RCV INT (interrupt) to be set. The

 

 

RCV_BAD bit of the Bank 1 Control Register controls

 

 

whether or not to generate interrupts when bad CRC

 

 

packets are received.

 

 

 

5

SERVICE INTERRUPT - Read the Interrupt Status

 

 

Register and determine if RCV INT is set. The next

 

 

receive packet is at receive area. (Its packet number

 

 

can be read from the FIFO Ports Register). The

 

 

software driver can process the packet by accessing

 

 

the RX area, and can move it out to system memory

 

 

if desired. When processing is complete the CPU

 

 

issues the REMOVE AND RELEASE FROM TOP OF

 

 

RX command to have the MMU free up the used

 

 

memory and packet number.

 

 

 

 

SMSC LAN91C111 REV C

87

Revision 1.91 (08-18-08)

DATASHEET