SMSC LAN91C111 CSMA/CD, Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

MII External

Signals

EECS EESK EEDO EEDI
EEPROM	100BASE-TX
CONTROL
	TRANSMITTER

RBIAS

	4B5B	SCRAMBLER	MLT3
TXD[3:0]	ENCODER		ENCODER
TX_ER
TXEN100
TX25

SWITCHED	LP	+
CURRENT		-
	FILTER
SOURCE
CLOCK
GEN
(PLL)

TPO+ TPO-

CSMA/CD To MII External Signals

CRS100 COL100

RXD[3:0]

RX_ER RX_DV

RX25

COLLISION

MANCHESTER

10BASE-T TRANSMITTER

ROM

CLOCK GEN (PLL)

SQUELCH

			+
DAC		LP
	FILTER		-

100BASE-TX
	RECEIVER
		+/- Vth

		4B5B	DESCRAMBL	CLOCK &
		DECODER	ER	DATA
				RECOVERY
				AUTO
MII				NEGOTIATION
	MDI			& LINK
SERIAL	MCLK
Manage	MDO
-ment
				SQUELCH
MII				CLOCK &
				DATA
				Recovery
				(Manchester
				Decoder)
Power	PHY	AUTONEG
On
	CONTROLS	LOGIC
Reset

	MLT	+				ADAPTIVE
ENCODER			+		EQUALIZER
		-
10BASE-T
RECEIVER
				+/- Vth
		+						LP
		+
							FILTER
		-
									Multiplexer
									S		D
									S
			nPLED[0-5]						C	C C	EN
											B
									Multiplexer
			LS[2-0]A
	LED								S		D
Control									S
									C	C C	EN
											B

LS[2-0]B

TPI+ TPI-

LED

LED

Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram

SMSC LAN91C111 REV C 13 Revision 1.91 (08-18-08)

DATASHEET