Appendix C Functional Description C-35
■One 64-bit merge bufferused to perform partial DVMA write in consistent mode.
The merge buffer participates in the UPAcoherence protocol.
■Twoseparate 16-entry streaming caches, one for each bus segment, for
accelerating some kinds of PCI DVMA activity.Single IOMMU with
16-entry TLB for mapping DVMA addresses for both buses (IOMMU used to
translate 32-bit or 64-bit PCI addresses into 41-bit UPAaddresses).
■An IOMMU used to translate 32- or 64-bit PCI addresses into 41-bit UPA
addresses. The IOMMU is shared between both PCI busses.
■A mondo-vector dispatch unit for delivering interrupt requests to CPU modules,
including support for PCI interrupts from up to six slots, as well as interrupts
from on-board I/O devices.
■Two32-bit counters.
C.1.15.5 FBC
The frame buffer controller (FBC) ASIC is the graphics draw ASIC that provides
interface between the UPAand the 3DRAM. The FBC ASIC provides 2D and 3D
graphics draw acceleration. The FBC resides on the UPAgraphics card, not on the
Ultra 60 motherboard.
Highlights of the FBC ASIC features include:
■UPAslave device with write-mostly philosophy
■Supports single buffered and DBZ configurations
■Interfaces with 3DRAM to achieve accelerated graphics performance
■Supports frame buffer-to-frame buffer copy
■Supports viewport clipping, picking, and pixel processing
■Supports byte, plane masks, raster operations, blend operations, and conditional
writes in 3DRAM
■83.3-MHz UPAoperation and 75-MHz 3DRAM operation
■3.3-Vdc and 5-Vdc (for RAMDAC ASIC) supply voltage
C.1.15.6 RISC
The reset, interrupt, scan, and clock (RISC) ASIC implements four functions: reset,
interrupt, scan, and clock. Generation and stretching of the reset pulse is performed
in this ASIC. Interrupt logic concentrates 42 different interrupt sources into a 6-bit
code, which communicates with the PSYCHO+ ASIC. It also integrates a JTAG
controller.
Highlights of the RISC ASIC features include: