Sun Microsystems 60 - page 254

Glossary-4 Sun Ultra 60 Service Manual •August 2001
UPA UltraSPARCport architecture. Provides processor-to-memory interconnection.
UPAAD0 UPAaddress bus 0. Provides data interface between CPU module 0 and the
QSC ASIC.
UPAAD1 UPAaddress bus 1. Provides data interface between CPU module 1 and the
QSC ASIC.Supports slave UPAconnection to the expansion slot for graphics
capability.
UPAAD2 UPAaddress bus 2. Provides data interface between QSC ASIC and the U2P
ASIC.
UPAAD3 UPAaddress bus 3. Provides data interface between QSC ASIC and the UPA
graphics.
UPADATA0 UPAdata bus 0. Provides 144-bit-wide data bus between the XB9+ ASIC and
CPU module 0.
UPADATA1 UPAdata bus 1. Provides 144-bit-wide data bus between the XB9+ ASIC and
the UPAgraphics.
UPADATA2 UPAdata bus 2. Provides 64-bit-wide data bus between the XB9+ ASIC and
CPU module 0.
UPADATA3 UPAdata bus 3. Provides 72-bit-wide data bus between the XB9+ ASIC and the
U2P ASIC.
UTP Unshielded twisted-pair.
VIS Visualinstruction set.
Vrms Voltsroot-mean-square.