Sun Microsystems 60 service manual QSC Asic

UPA UltraSPARC port architecture. Provides processor-to-memory interconnection.

UPA AD 0 UPA address bus 0. Provides data interface between CPU module 0 and the

QSC ASIC.

UPA AD 1 UPA address bus 1. Provides data interface between CPU module 1 and the QSC ASIC.Supports slave UPA connection to the expansion slot for graphics capability.

UPA AD 2 UPA address bus 2. Provides data interface between QSC ASIC and the U2P ASIC.

UPA AD 3 UPA address bus 3. Provides data interface between QSC ASIC and the UPA graphics.

UPA DATA 0 UPA data bus 0. Provides 144-bit-wide data bus between the XB9+ ASIC and CPU module 0.

UPA DATA 1 UPA data bus 1. Provides 144-bit-wide data bus between the XB9+ ASIC and the UPA graphics.

UPA DATA 2 UPA data bus 2. Provides 64-bit-wide data bus between the XB9+ ASIC and CPU module 0.

UPA DATA 3 UPA data bus 3. Provides 72-bit-wide data bus between the XB9+ ASIC and the U2P ASIC.

UTP Unshielded twisted-pair.

VIS Visual instruction set.

Vrms Volts root-mean-square.

Glossary-4Sun Ultra 60 Service Manual • August 2001