Sun Microsystems 60 service manual Code Example 3-1 diag-levelVariable Set to max

CODE EXAMPLE 3-1 diag-levelVariable Set to max (Continued)

2> <00> DMMU TLB Tag Access Test

2> <00> DMMU TLB RAM Access Test

2> <00> IMMU TLB Tag Access Test

2> <00> IMMU TLB RAM Access Test 2> <00> Probe Ecache 2>INFO:CPU 296 MHz: 2048KB Ecache 2> <00> Ecache RAM Addr Test

2> <00> Ecache Tag Addr Test 2> <00> Ecache Tag Test

2> <00> Invalidate Ecache Tags

2> <00> Map PROM/STACK/NVRAM in DMMU 2> <00> Update Slave Stack/Frame Ptrs 0> <00> DMMU Hit/Miss Test

0> <00> IMMU Hit/Miss Test

0> <00> DMMU Little Endian Test 0> <00> IU ASI Access Test

0> <00> FPU ASI Access Test

2> <00> DMMU Hit/Miss Test

2> <00> IMMU Hit/Miss Test

2> <00> DMMU Little Endian Test 2> <00> IU ASI Access Test

2> <00> FPU ASI Access Test 2> <00> Dcache RAM Test

2> <00> Dcache Tag Test

2> <00> Icache RAM Test

2> <00> Icache Tag Test

2> <00> Icache Next Test

2> <00> Icache Predecode Test 0> <1f> Init Psycho

0> <1f> PIO Read Error, Master Abort Test 0> <1f> PIO Read Error, Target Abort Test 0> <1f> PIO Write Error, Master Abort Test 0> <1f> PIO Write Error, Target Abort Test 0> <1f> Timer Increment Test

0> <1f> Consistent DMA UE ECC Rd Err Lpbk Test 0> <1f> Pass-Thru DMA UE ECC Rd Err Lpbk Test 0> <00> Copy Post to Memory

0> <00> Ecache Thrash Test 0> <00> Init Memory

0> <00> Memory Addr w/ Ecache Test 0>INFO:128MB Bank 0

0>INFO: 0MB Bank 1

0>INFO: 0MB Bank 2

0>INFO: 0MB Bank 3

0> <00> Block Memory Addr Test 0>INFO:128MB Bank 0

0>INFO: 0MB Bank 1

3-8Sun Ultra 60 Service Manual • August 2001