CODE EXAMPLE 3-1 diag-levelVariable Set to max (Continued)

0>INFO: 0MB Bank 2

0>INFO: 0MB Bank 3

0> <00> ECC Memory Addr Test 0>INFO:128MB Bank 0 0>INFO: 0MB Bank 1 0>INFO: 0MB Bank 2 0>INFO: 0MB Bank 3

0> <00> Memory Status Test 0>INFO:128MB Bank 0 0>INFO: 0MB Bank 1 0>INFO: 0MB Bank 2 0>INFO: 0MB Bank 3

0> <00> V9 Instruction Test

0> <00> CPU Tick and Tick Compare Reg Test 0> <00> CPU Soft Trap Test

0> <00> CPU Softint Reg and Int Test 2> <00> V9 Instruction Test

2> <00> CPU Tick and Tick Compare Reg Test 0> <1f> Init Psycho

0> <1f> Psycho Cntl and UPA Reg Test 0> <1f> Psycho DMA Scoreboard Reg Test 0> <1f> Psycho Perf Cntl Reg Test

0> <1f> PIO Decoder and BCT Test 0> <1f> PCI Byte Enable Test

0> <1f> Counter/Timer Limit Regs Test 0> <1f> Timer Reload Test

0> <1f> Timer Periodic Test

0> <1f> Mondo Int Map (short) Reg Test 0> <1f> Mondo Int Set/Clr Reg Test

0> <1f> Psycho IOMMU Regs Test

0> <1f> Psycho IOMMU RAM Address Test 0> <1f> Psycho IOMMU CAM Address Test 0> <1f> IOMMU TLB Compare Test

0> <1f> IOMMU TLB Flush Test

0> <1f> Stream Buff A Control Reg Test 0> <1f> Psycho ScacheA Page Tag Addr Test 0> <1f> Psycho ScacheA Line Tag Addr Test 0> <1f> Psycho ScacheA RAM Addr Test

0> <1f> Psycho ScacheA Error Status NTA Test 0> <1f> Psycho ScacheB Page Tag Addr Test 0> <1f> Psycho ScacheB Line Tag Addr Test 0> <1f> Psycho ScacheB RAM Addr Test

0> <1f> Psycho ScacheB Error Status NTA Test 0> <1f> PBMA PCI Config Space Regs Test

0> <1f> PBMA Control/Status Reg Test 0> <1f> PBMA Diag Reg Test

0> <1f> PBMB PCI Config Space Regs Test

Chapter 3 Power-On Self-Test 3-9

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Sun Microsystems 60 service manual Power-On Self-Test