C-4 Sun Ultra 60 Service Manual • August 2001
C.1.1 UPA Interconnect
The UltraSPARCport architecture (UPA) provides a packet-based interconnect
between the UPAclients: CPU modules, PSYCHO+ ASIC, UPA graphics cards.
Electrical interconnection is provided through four addressbuses and four data
buses. See FIGUREC-2.
The four address buses are:
■UPAaddress bus 0 (UPA_AD0)
■UPAaddress bus 1 (UPA_AD1)
■UPAaddress bus 2 (UPA_AD2)
■UPAaddress bus 3 (UPA_AD3)
The four data buses are:
■UPAdata bus 0 (UPA_DATA0)
■UPAdata bus 1 (UPA_DATA1)
■UPAdata bus 2 (UPA_DATA2)
■UPAdata bus 3 (UPA_DATA3)
UPA_AD0and UPA_AD1 connect the Marvin ASIC to the CPU modules and the
PSYCHO+ ASIC. UPA_AD2connects the Marvin ASIC to the PSYCHO+ ASIC.
UPA_AD3connects the Marvin ASIC to the UPA graphics.
Twoprocessor data buses (UPA_DATA0 and UPA_DATA1)are bidirectional 144-bit
data buses (128 bits of data and 16 bits of ECC). UPA_DATA0and UPA_DATA1
connect each CPU module to the K9+ ASIC. The I/O data buses (UPA_DATA2and
UPA_DATA3)are bidirectional data buses. UPA_DATA2is a 64-bit data bus that
connects the PSYCHO+ ASIC and the UPAgraphics. UPA_DATA3 is a 72-bit data
bus (64 bits of data and eight bits of ECC) that connects the K9+ ASIC to the
PSYCHO+ ASIC.
TABLEC-1 lists UPA port identification assignments. FIGURE C-2 illustrates how the
UPAaddress and data buses are connected between the UPA and the UPA clients.
TABLEC-1 UPAPort Identification Assignments
UPASlot Number UPAPort ID <4:0>
CPU module slot 0 0x0
CPU module slot 1 0x1
PSYCHO+ ASIC 0x1F