CODE EXAMPLE 3-1 diag-levelVariable Set to max (Continued)

0> <1f> PBMB Control/Status Reg Test 0> <1f> PBMB Diag Reg Test

0> <00> FPU Regs Test

0> <00> FPU Move Regs Test

0> <00> FPU State Reg Test

0> <00> FPU Functional Test 0> <00> FPU Trap Test

0> <00> DMMU Primary Context Reg Test 0> <00> DMMU Secondary Context Reg Test 0> <00> DMMU TSB Reg Test

0> <00> DMMU Tag Access Reg Test

0> <00> DMMU VA Watchpoint Reg Test 0> <00> DMMU PA Watchpoint Reg Test 0> <00> IMMU TSB Reg Test

0> <00> IMMU Tag Access Reg Test

0> <00> DMMU TLB Tag Access Test

0> <00> DMMU TLB RAM Access Test 0> <00> Dcache RAM Test

0> <00> Dcache Tag Test

0> <00> Icache RAM Test

0> <00> Icache Tag Test

0> <00> Icache Next Test

0> <00> Icache Predecode Test 2> <00> FPU Regs Test

2> <00> FPU Move Regs Test

2> <00> FPU State Reg Test

2> <00> FPU Functional Test 2> <00> FPU Trap Test

2> <00> DMMU Primary Context Reg Test 2> <00> DMMU Secondary Context Reg Test 2> <00> DMMU TSB Reg Test

2> <00> DMMU Tag Access Reg Test

2> <00> DMMU VA Watchpoint Reg Test 2> <00> DMMU PA Watchpoint Reg Test 2> <00> IMMU TSB Reg Test

2> <00> IMMU Tag Access Reg Test

2> <00> DMMU TLB Tag Access Test

2> <00> DMMU TLB RAM Access Test

0> <00> CPU Addr Align Trap Test 0> <00> DMMU Access Priv Page Test

0> <00> DMMU Write Protected Page Test 0> <1f> Init Psycho

0> <1f> Pri CE ECC Error Test 0> <1f> Pri UE ECC Error Test

0> <1f> Pri 2 bit w/ bit hole UE ECC Err Test 0> <1f> Pri 3 bit UE ECC Err Test

0> <1f> Streaming DMA UE ECC Rd Err Ebus Test

3-10Sun Ultra 60 Service Manual • August 2001

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Image 44
Sun Microsystems 60 service manual Code Example 3-1 diag-levelVariable Set to max