Sun Microsystems 60 service manual Phy

FIGURE C-8illustrates MII being used to interconnect both integrated circuits and circuit assemblies. This enables separate signal transmission paths to exist between the reconciliation sublayer, embedded in the Cheerio ASIC, and a local PHY IC, and between the reconciliation sublayer and a remote PHY IC. The unidirectional paths between the reconciliation sublayer and the local PHY IC are composed of sections A1, B1, C1 and D1. The unidirectional paths between the reconciliation sublayer and the remote PHY IC are composed of sections A2, B2, C2, and D2.

Reconciliation

sublayer

(Cheerio ASIC)

A2		B2
A1	B1
	PHY	PHY
	(local)	(remote)
D1	C1
D2		C2

FIGURE C-8MII Port Timing Model

Appendix C Functional Description C-27