CODE EXAMPLE 3-1 diag-levelVariable Set to max (Continued)

0> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit (prev wr) Lpbk Test 0> <1f> Stream DMA Wr, IOMMU miss, Scache Miss Ebus Test

0> <1f> Stream DMA Wr, IOMMU miss, Scache Miss Lpbk Test 0> <1f> Stream DMA Wr, IOMMU hit, Scache Miss Ebus Test 0> <1f> Stream DMA Wr, IOMMU hit, Scache Miss Lpbk Test

0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev rd) Hit Ebus Test 0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev rd) Hit Lpbk Test 0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev rd) Hit Ebus Test 0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev rd) Hit Lpbk Test 0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev wr) Hit Ebus Test 0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev wr) Hit Lpbk Test 0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev wr) Hit Ebus Test 0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev wr) Hit Lpbk Test 0> <1f> Pass-Thru DMA Rd, Ebus device Test

0> <1f> Pass-Thru DMA Rd, Loopback Mode Test 0> <1f> Pass-Thru DMA Wr, Ebus device Test 0> <1f> Pass-Thru DMA Wr, Loopback Mode Test

0> <1f> Consist DMA Rd, IOMMU LRU Lock Ebus Test 0> <1f> Consist DMA Rd, IOMMU LRU Lock Lpbk Test

0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache LRU Lock Ebus Test 0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache LRU Lock Lpbk Test 0> <1f> Stream DMA Rd, IOMMU miss, Scache LRU Lock Ebus Test

0> <1f> Stream DMA Rd, IOMMU Miss, Scache LRU Lock Lpbk Test 0> <1f> Stream DMA Rd, IOMMU Hit, Scache LRU Lock Ebus Test 0> <1f> Stream DMA Rd, IOMMU Hit, Scache LRU Lock Lpbk Test 0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache Miss Ebus Test 0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache Miss Lpbk Test 0> <1f> Consist DMA Wr, IOMMU LRU Locked Ebus Test

0> <1f> Consist DMA Wr, IOMMU LRU Lock Lpbk Test

0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache LRU Lock Ebus Test 0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache LRU Lock Lpbk Test 0> <1f> Stream DMA Wr, IOMMU Miss, Scache LRU Lock Ebus Test

0> <1f> Stream DMA Wr, IOMMU Miss, Scache LRU Lock Lpbk Test 0> <1f> Stream DMA Wr, IOMMU Hit, Scache LRU Lock Ebus Test 0> <1f> Stream DMA Wr, IOMMU Hit, Scache LRU Lock Lpbk Test 0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache Miss Ebus Test 0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache Miss Lpbk Test 0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache(prev rd) Hit Ebus Test

0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache(prev rd) Hit Lpbk Test

0> <00> Init Memory 0>INFO:128MB Bank 0 0>INFO: 0MB Bank 1 0>INFO: 0MB Bank 2 0>INFO: 0MB Bank 3

0> <00> Memory w/ Ecache Test

3-12Sun Ultra 60 Service Manual • August 2001

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Image 46
Sun Microsystems 60 service manual Code Example 3-1 diag-levelVariable Set to max