Appendix C Functional Description C-5
FIGUREC-2 UPA Address and Data Buses Functional Block Diagram
C.1.2 System ControllerThe system controller ASIC, also known as Marvin, implements the central resource
for the UPAprotocol. It performs the following functions:
■Accepts UPArequest packets from the three masters; two processors and
PSYCHO+, and routes them to the correct slave destination.
■Maintains cache coherence between the merger buffer in PSYCHO+ and the
processor cache.
■Implements blocking rules that guarantee that all requests are properly ordered.
■Controls the K9+ ASIC, and so controls the flow of data throughthe system.
■Contains a memory controller that supplies address and control lines to memory.
■Receives and distributes resets to all of the UPAclients in the system.
■Contains logic for waking up the processor in EnergyStar mode.
Marvin
UPA_ADDRBUS0
UPA_ADDRBUS1
UPA_AD0
PSYCHO+
UPA
UPA
UPA_AD3
<35:0>
<28:0>
UPA_DATA0
XB9+
P Bus
I Bus
UPA_DATA3
UPA_AD2
UPA_AD3
UPA_DATA2
UPA_DATA2
ASIC ASIC
ASIC
graphics 0
graphics 1
CPU
module
CPU
module
UPA_AD1 UPA_DATA1
0
1