Sundance Technology

ST201

PRELIMINARY draft 2

DMACTRL

 

Class

I/O Registers, DMA

Base Address

IoBaseAddress register value

Address Offset

0x00

Access Mode

Read/Write

Width

32 bits

DMACtrl controls some of the bus master functions in the RxDMA and TxDMA engines, and contains sta- tus bits. DMACtrl is cleared by a reset.

BIT

0

1

2

3

4

7..5

8

9

10

11

13..12

14

BIT NAME

RxDMAHalted

TxDMACmplReq

TxDMAHalted

RxDMAComplete

TxDMAComplete

Reserved

RxDMAHalt

RxDMAResume

TxDMAHalt

TxDMAResume

Reserved

TxDMAInProg

BIT DESCRIPTION

This read-only bit is set whenever RxDMA is halted by setting the RxD- MAHalt bit or an implicit halt due to fetching a RFD with RxDMACom- plete in ReceiveFrameStatus already set. Cleared by setting the RxDMAResume bit.

This read-only bit is set to the value from the TxDMAIndicate field in the TFC of the current TFD.

This read-only bit is set whenever TxDMA is halted by setting the TxD- MAHalt bit. Cleared by setting the TxDMAResume bit.

This read-only bit is the same as RxDMAComplete in IntStatus. This bit is different from the RxDMAComplete bit in RxDMAStatus, which is a real time indication of frame RxDMA completion and is cleared when a new frame RxDMA begins. This bit is latched once a frame RxDMA completion has occurred. This bit is cleared by acknowledgment to the RxDMAComplete bit in the IntStatus register.

This read-only bit is the same as TxDMAComplete in IntStatus. This bit is cleared by acknowledgment to the TxDMAComplete bit in the IntSta- tus register.

Reserved for future use. Should be set to 0.

Whenever this bit is set, the RxDMA is halted. This bit is self-clearing and writing a 0 into this bit is ignored.

Whenever this bit is set, the RxDMA is resumed. This bit is self-clear- ing and writing a 0 into this bit is ignored.

Whenever this bit is set, the TxDMA is halted. This bit is self-clearing and writing a 0 into this bit is ignored.

Whenever this bit is set, the TxDMA is resumed. This bit is self-clearing and writing a 0 into this bit is ignored.

Reserved for future use. Should be set to 0.

This read-only bit indicates that a TxDMA operation is in progress. This bit is primarily used by drivers in an under run recovery routine since the driver needs waits for this bit to be cleared before issuing the TxRe- set to clear the under run condition. Before checking TxDMAInProg, issue TxDMAHalt to ensure that TxDMAInProg is not set as a result of the ST201 being in a polling mode.

69

Page 69
Image 69
Sundance Spas ST201 manual Dmactrl, Bit