Manuals / Sundance Spas / Computer Equipment / Network Card

Sundance Spas ST201 manual PIN Diagram

Models: ST201

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DC Characteristics Block Diagram Carriersenseerrors Latencytimer Dimension PCI Configuration Registers Reserved ResetPolarity Media Access Control Eeprom Commands Temperature Range

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Sundance Technology

PIN DIAGRAM

ST201

PRELIMINARY draft 2

4

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Sundance Spas ST201 manual PIN Diagram

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Contents

Features General Description Block Diagram Temperature Range Ordering InformationPackage Type Device NUMBER/DESCRIPTION PIN Diagram PIN Designations PIN Descriptions PIN Name Rstn Pciclk Gntn Idsel Intan Wake Reqn Txen Output Txclk Input MII InterfaceRxclk Input Rxer Rxdv CRS PHY Interface Eeprom InterfaceExpansion ROM Interface LED Drivers CLK25 Power and GroundMiscellaneous Media Access Control Acronyms and GlossaryStandards Compliance Functional Description PCI BUS Interface Txdma LogicTxfifo Rxdma Logic Expansion ROM Interface OperationInitialization Register Programming Field Length Bytes TypeOpcode Pause Time PAD Txdma and Frame Transmission Host System Memory TFD Sundance Technology ST201 Preliminary draft Frame Reception and Rxdma Host System Memory RxDMA List Shown in Ring Configuration Host System Memory RFD Interrupts Statistics PCI BUS Master OperationTransmit Statistics Receive Statistics Power Management Txfifo Example Psuedo Packet Host System Related Information Programming the MII Management Interface Eeprom Commands Adding TFD’S to the END of the Txdmalist Adapter Txdma SequenceInserting a TFD AT the Head of the Txdmalist Rxdma Sequence Transmit Interrupt OptimizationsWake Event Programming Sundance Technology ST201 Wake Event Registers and Data Structures DMA Data Structures Txdmafragaddr BITBIT Name BIT Description Txdmafraglen Txdmanextptr Txframecontrol Rxdmanextptr Rxframestatus BIT BIT Name Rxdmafragaddr Rxdmafraglen Wake Event Data Structures ST201 Txfifo Pseudopattern Terminator Pseudocrc Magicsyncstream Magicsequence Registers ST201 I/O Register Layout Asicctrl Sundance Technology 19 DMA Debugctrl GPIO0 GPIO1 Hashtable Macctrl Sundance Technology ST201 Loopback Modes Maxframesize Receivemode Stationaddress Txframeid Txstatus Wakeevent Fifoctrl Rxearlythresh Txreleasethresh Txstartthresh Countdown Intenable Intstatus RxDMAComplete Reserved Intstatusack Sundance Technology Dmactrl BIT 29..24 MasterAbort Rxdmaburstthresh Rxdmalistptr Rxdmastatus BIT 22..21 31..25 Rxdmapollperiod Rxdmaurgentthresh Txdmaburstthresh Txdmalistptr Txdmapollperiod Txdmaurgentthresh Eepromctrl Eepromdata Expromaddr Expromdata Phyctrl Statistics Broadcastframesreceivedok Broadcastframestransmittedok Carriersenseerrors Framesabortedduetoxscolls Frameslostrxerrors Framesreceivedok Framestransmittedok Frameswithdeferredxmission Frameswithexcessivedeferal Latecollisions Multicastframesreceivedok Multicastframestransmittedok Multiplecollisionframes Octetsreceivedok Octetstransmittedok Singlecollisionframes PCI Configuration Registers ST201 PCI Register Layout Cachelinesize Capptr Classcode Configcommand Configstatus Deviceid Exprombaseaddress Headertype Interruptline Interruptpin Iobaseaddress Latencytimer Maxlat Membaseaddress Mingnt Revisionid Subsystemid Subsystemvendorid Vendorid Capid Nextitemptr Powermgmtcap Powermgmtctrl Eeprom Data Format Eeprom Data Layout Configparm 0x00, address written to EepromCtrl register 0x10, 0x12 Asicctrl 14..8 Reserved ResetPolarity 0x00, address written to Address Offset 0x06 Absolute Maximum Ratings Operating Ranges DC Characteristics Pins PCI Interface RSTN, PCICLK, GNTN, Idsel PIN Type OD8 Open Drain Output Buffer 138 Switching Characteristics Parameter Test Conditions Symbol Description PCI InterfaceExpansion ROM Interface Read Expansion ROM Interface Load Parameter Test Conditions Eeprom Interface MINMII Interface Transmit MII Interface Receive 400 160 Rstn Pciclk Bussed Signals Reqn Gntn ANY Signal PCI Switching Characteristics Eeprom Switching Characteristics Eesk Eedi MII Switching Characteristics Rxer Rxdv Rxclk Mdio Physical Dimensions

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