Sundance Technology

ST201

PRELIMINARY draft 2

Systems using the ST201 can be programmed to generate an interrupt based upon the number of bytes that have been received in a frame. The RxEarlyThresh register sets the value for early receive threshold. As soon as the number of bytes that have been received is greater than the value in RxEarlyThresh register, the ST201 will generate a RxEarly interrupt, if it is enabled, to the host. The RxEarly interrupt will only occur when the frame being received is the top frame, i.e., can be trans- ferred by the host during reception. The RxEar- lyThresh mechanism will cause one RxEarly interrupt per frame. The host system can program any value greater than or equal to 0x08 into RxEar- lyThresh. The ST201 needs a minimum of 8 frame bytes to perform destination address filtering before generating an RxEarly interrupt. The value in RxEarlyThresh may also determine how many bytes of a frame must be received before RxDMA transfers for the frame are allowed to begin. If RxEarlyEnable in DMACtrl is set, a frame becomes eligible to start RxDMA when RxEarlyThresh bytes have been received. Setting RxEarlyThresh too low will cause the host to respond to the interrupt before the entire receive frame header has been received. Setting RxEarlyThresh too high will intro- duce unnecessary delays in the system’s receive response sequence. When RxEarlyThresh is set to a value that is greater than the length of the received frame, a RxComplete interrupt will occur at the completion of frame reception rather than a RxEarly interrupt. If the host system is particularly slow in responding to a RxEarly interrupt, then it is likely that the frame will have been completely received by the time the driver examines the ST201. In this case, RxEarly will be overridden by RxComplete. RxEarly is cleared when RxComplete becomes set, hence they are mutually exclusive. In order to prevent spurious interrupts, RxComplete should only be disabled if RxEarly is also disabled.

In some host systems, it may be desirable to copy received frame data out of the scatter buffer to the protocol buffer while the frame is still being trans- ferred by RxDMA. The RxDMAStatus register is provided for this purpose. If the host system sets the RxDMAHalt bit in the DMACtrl register, reads the RxDMAListPtr register and the RxDMAStatus register, then sets the RxDMAResume bit in the DMACtrl register, the host system can determine how much of the frame has been transferred by RxDMA. The RxDMAStatus register indicates the number of bytes transferred by RxDMA for the cur- rent RFD pointed to by the RxDMAListPtr register.

The host system can then perform memory copies out of the RFD buffer in parallel with the RxDMA operation.

INTERRUPTS

The term “interrupt”is used loosely to refer to inter- rupts and indications. An interrupt is the actual assertion of the hardware interrupt signal on the PCI bus. An indication, or a set bit in the IntStatus register, is the reporting of any event enabled by the host. The host system will configure the ST201 to generate an interrupt for any indication that is of interest to it. There are 10 different types of inter- rupt indications that can be generated by the ST201. The IntEnable register controls which of the 10 indication bits can assert a hardware inter- rupt. In order for an indication bit to be allowed to generate an interrupt, its corresponding bit-position in IntEnable must be set. When responding to an interrupt, the host reads the IntStatus register to determine the cause of the interrupt. The least sig- nificant bit of IntStatus, InterruptStatus, is always set whenever any of the interrupts are asserted. InterruptStatus must be explicitly acknowledged (cleared) by writing a 1 into the bit in order to pre- vent spurious interrupts on the host bus.

Interrupts are acknowledged by the host carrying out various actions specific to each interrupt. These actions are as follows:

HostError, acknowledged by issuing the appropri- ate resets

TxComplete, acknowledged by writing to TxSta- tus

RxComplete, acknowledged automatically by the hardware

UpdateStats, acknowledged by reading statistics registers

InterruptStatus, acknowledged by writing a 1 into this bit

RxEarly, acknowledged by writing a 1 into this bit

IntRequested, acknowledged by writing a 1 into this bit

LinkEvent, acknowledged by writing a 1 into this bit

TxDMAComplete, acknowledged by writing a 1 into this bit

RxDMAComplete, acknowledged by writing a 1 into this bit

MACControlFrame, acknowledged by writing a 1 into this bit

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Sundance Spas ST201 manual Interrupts