Sundance Technology
ST201
PRELIMINARY draft 2
INTENABLE |
|
Class | I/O Registers, Interrupt |
Base Address | IoBaseAddress register value |
Address Offset | 0x4c |
Access Mode | Read/Write |
Width | 16 bits |
Enables individual interrupts as specified in the IntStatus register. Setting a bit in IntEnable will allow the specific source to generate an interrupt on the PCI bus. IntEnable is cleared upon reset. IntEnable is also cleared by a read of IntStatusAck.
BIT
0
1
2
3
4
5
6
7
8
9
10
15..11
BIT NAME
Unused
EnHostError
EnTxComplete
EnMACControl- Frame
EnRxComplete
EnRxEarly
EnInRequested
EnUpdateStats
EnLinkEvent
EnTxDMACom- plete
EnRxDMACom- plete
Unused
BIT DESCRIPTION
This bit will be ignored.
Enables the HostError interrupt.
Enables the TxComplete interrupt.
Enables the MACControlFrame interrupt.
Enables the RxComplete interrupt.
Enables the RxEarly interrupt.
Enables the InRequested interrupt.
Enables the UpdateStats interrupt.
Enables the LinkEvent interrupt.
Enables the TxDMAComplete interrupt.
Enables the RxDMAComplete interrupt.
These bits bill be ignored.
64
