Sundance Spas ST201 PCI BUS Interface, Txdma Logic, Txfifo, Rxdma Logic, Rxfifo, Eeprom Interface

Sundance Technology

ST201

PRELIMINARY draft 2

PCI BUS INTERFACE

The PCI Bus Interface (PBI) implements the proce- dures and algorithms needed to link the ST201 to a PCI bus. The ST201 can be either a PCI bus mas- ter or slave. The PBI is also responsible for manag- ing the DMA interfaces and the host processors access to the ST201 registers. Arbitration logic within the PBI block accepts bus requests from the TxDMA Logic and RxDMA Logic. The arbiter ser- vices the four requests in the fixed priority order of:

1.RxDMA Urgent Request

2.TxDMA Urgent Request

3.RxDMA Request

4.TxDMA Request

The PBI also manages interrupt generation for a host processor.

TXDMA LOGIC

The ST201 supports a multi-frame, multi-fragment DMA gather process. Descriptors representing frames are built and linked in system memory by a host processor. The TxDMA Logic is responsible for transferring the multi-fragment frame data from the host memory into the TxFIFO.

The TxDMA Logic monitors the amount of free space in the TxFIFO, and uses this value to decide when to request a TxDMA. A TxDMABurstThresh register is used to delay the bus request until there is enough free space in the TxFIFO for a long burst.

To prevent a TxFIFO under run condition the TxDMA logic forwards an urgent request to the DMA arbiter, regardless of the TxDMABurstThresh constraint, when the number of occupied bytes in the TxFIFO drops below the value in TxDMAUr- gentThresh register.

TXFIFO

The ST201 uses 2K bytes of transmit data buffer between the TxDMA Logic and Transmit MAC. When the TxDMA logic determines there is enough space available in the TxFIFO, the TxDMA Logic will move any pending frame data into the TxFIFO. The TxReleaseThresh register value determines the amount of data which must be transmitted out of the TxFIFO before the FIFO memory space occupied by that data can be released for use by another frame.

A TxReleaseError occurs when a frame experi- ences a collision after the TxFIFO release thresh- old has been crossed. The ST201 will not be able to retransmit this frame from the TxFIFO and the

complete frame must be transferred from the host system memory to the TxFIFO again by TxDMA Logic.

RXDMA LOGIC

The ST201 supports a multi-frame, multi-fragment DMA scatter process. Descriptors representing frames are built and linked in system memory by a host processor. The RxDMA Logic is responsible for transferring the multi-fragment frame data from the RxFIFO to the host memory.

The RxDMA Logic monitors the number of bytes in the RxFIFO. After a number of bytes have been received, the frame is “visible”. A frame is visible if:

•The frame being received is determined not to be a runt, AND

•The number of frame bytes received has exceeded the value in the RxEarlyThresh reg- ister (if enabled), OR

•The entire frame has been received

After a frame becomes visible, the RxDMA Logic will issue a request to the DMA arbiter when the number of bytes in the RxFIFO is greater than the value in the RxDMABurstThresh. To prevent receive overruns, a RxDMA Urgent Request is made when the amount of free space in the RxFIFO falls below the value in RxDMAUrgent- Thresh.

RXFIFO

The ST201 uses 2K bytes of receive data buffer between the Receive MAC and RxDMA Logic. When the RxDMA Logic determines the number of bytes in the RxFIFO is greater than the value in RxEarlyThresh register, the ST201 will generate a RxEarly interrupt (if enabled) to the host. The val- ues in RxEarlyThresh and RxDMABurstThresh also determine how many bytes of a frame must be received into RxFIFO before RxDMA Logic is allowed to begin data transfer.

When RxEarlyThresh is set to a value that is greater than the length of the received frame, a RxComplete interrupt will occur at the completion of frame reception rather than a RxEarly interrupt.

EEPROM INTERFACE

The external serial EEPROM is used for non-vola- tile storage of such information as the node address, system ID, and default configuration set- tings. As part of initialization after system reset, the ST201 reads certain locations from the EEPROM and places the data into host-accessible registers.

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