Sundance Technology
BLOCK DIAGRAM
ST201
PRELIMINARY draft 2
PCI
RSTN 
PCICLK 
GNTN 
IDSEL 
INTAN 
WAKE 
REQN 
AD[31..0] 
CBEN[3:0] 
PAR 
FRAMEN 
IRDYN 
TRDYN 
DEVSELN 
STOPN 
PERRN 
SERRN 
VDET 
MISCELLANEOUS
GPIO0 
GPIO1 
RSTOUT 
X25I
X25O
CLK25 
POWER
VCC
GND
PCI Bus I/F
Status/Control
Registers
Tx |
| Tx |
| Tx |
DMA |
| FIFO |
| MAC |
|
|
|
|
|
Rx |
| Rx |
| Rx |
DMA |
| FIFO |
| MAC |
|
|
|
|
|
Statistic Registers
MII
TXD[3..0]
TXEN
TXCLK
RXD[3..0]
RXCLK
RXER
RXDV
CRS
COL
MDC 
MDIO
EEPROM
EEDO
EEDI
EESK
EECS
EXPANSION ROM
ED[7..0]
EA[15..0]
EWEN 
EOEN
PHY
PHYLNKN
PHYDPLXN 
PHYSPDN
LED
LEDPWRN
LEDLNKN
LEDDPLXN 
LEDSPDN
FIGURE 1: ST201 Block Diagram
2
