Sundance Technology

ST201

PRELIMINARY draft 2

STATISTICS

The ST201 implements 16 statistics counters of various widths. Each statistic implemented com- plies to the corresponding definition given in the IEEE 802.3 standard. Setting the StatisticsEnable bit in the MACCtrl register enables the gathering of statistics. Reading a statistics register will clear the read register. Statistic registers may be read with- out disabling statistics gathering. For diagnostics and testing purposes, the host system may write a value to a statistic register, in which case the value written is added to the current value of the register. Whenever one or more of the statistics registers reaches 75% of its maximum value, an Updat- eStats interrupt is generated. Reading that statis- tics register will acknowledge the UpdateStats interrupt. A summary of the transmit and receive statistics follows. Detailed descriptions of the sta- tistic registers related to data transmission and reception can be found in the Registers and Data Structures section.

TRANSMIT STATISTICS

•FramesTransmittedOk: The number frames of all types transmitted without errors. Loss of carrier is not considered to be an error by this statistic.

•BroadcastFramesTransmittedOk: The number of frames with broadcast destination address that are transmitted without errors.

•MulticastFramesTransmittedOk: The number of frames with multicast destination address that are transmitted without errors.

•OctetsTransmittedOk: The number of total octets for all frames transmitted without error.

•FramesWithDeferredXmission: A count of frames whose transmission was delayed on it’s first attempt because network traffic.

•FramesWithExcessiveDeferral: If the transmis- sion of a frame has been deferred for an excessive period of time due to network traffic, the event is recorded in this statistic.

•SingleCollisionFrames: Frames that are transmit- ted without errors after one and only one colli- sion (including late collisions) are counted by this register.

•MultipleCollisionFrames: All frames transmitted without error after experiencing from 2 through 15 collisions (including late collisions) are counted here.

•LateCollisions: Every occurrence of a late colli- sion (there could be more than one per frame transmitted) is counted by this statistic.

•FramesAbortedDueToXSColls: If the transmis- sion of a frame had to be aborted due to excessive collisions, the event is recorded in

this statistic.

CarrierSenseErrors: Frames that were transmit- ted without error but experienced a loss of car- rier are counted by this statistic.

RECEIVE STATISTICS

FramesReceivedOk: Frames of all types that are received without error are counted here.

BroadcastFramesReceivedOk: Frames of broad- cast destination address that are received without error are counted here.

MulticastFramesReceivedOk: Frames of multi- cast destination address that are received without error are counted here.

OctetsReceivedOk: A total octet count for all frames received without error.

FramesLostRxErrors: This is a count of frames that would otherwise be received by the ST201, but could not be accepted due to an overrun condition in the RxFifo.

PCI BUS MASTER OPERATION

The ST201 supports all of the PCI memory com- mands and decides on a burst-by-burst basis which command to use in order to maximize bus efficiency. The list of PCI memory commands is shown below. For all commands, “read”and “write” are with respect to the ST201 (i.e. read implies the ST201 obtains information from an off-chip loca- tion, write implies the ST201 sends information to an off-chip location).

Memory Read (MR)

Memory Read Line (MRL)

Memory Read Multiple (MRM).

Memory Write (MW)

Memory Write Invalidate (MWI)

MR is used for all fetches of descriptor information. For reads of transmit frame data, MR, MRL, or MRM is used, depending upon the remaining num- ber of bytes in the fragment, the amount of free space in the TxFIFO, and whether the RxDMA Logic is requesting a bus master operation.

MW is used for all descriptor writes. Writes of receive frame data use either MW or MWI, depend- ing upon the remaining number of bytes in the frag- ment, the amount of frame data in the RxFIFO, and whether the TxDMA Logic is requesting a bus mas- ter operation.

The ST201 provides three configuration bits to control the use of advanced memory commands. The MWlEnable bit in the ConfigCommand config- uration register allows the host to enable or disable the use of MWI. The MWIDisable and MRLDisable bits in DMACtrl allow the host system the ability to

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Sundance Spas ST201 manual PCI BUS Master Operation, Transmit Statistics, Receive Statistics