Sundance Technology
ST201
PRELIMINARY draft 2
PHYCTRL |
|
Class | I/O Registers, External Interface Control |
Base Address | IoBaseAddress register value |
Address Offset | 0x5e |
Access Mode | Read/Write |
Width | 8 bits |
This register contains control bits for the MII Management Interface. The MII Management Interface is used to access registers in an MII PHY device. The Management Interface is a
BIT
0
1
2
3
4
5
6
7
BIT NAME
MgmtClk
MgmtData
MgmtDir
DisableClk25
PhyDuplexPolarity
PhyDuplexStatus
PhySpeedStatus
PhyLinkStatus
BIT DESCRIPTION
The MII Management Clock. This bit drives directly the management clock to the PHY device(s).
The MII Management Data bit. When the MgmtDir bit (below) is set, the value written to this bit is driven onto the MDIO signal. When Mgmt- Dir is cleared, data being driven by the PMD can be read from this bit.
The MII data direction control bit. Setting this bit causes ST201 to drive MDIO with the data bit written into MgmtData.
This bit is set to
Clearing this read/write bit will cause the PHYDPLXN input pin to be active low. The default value for this bit upon reset is cleared.
This
This
This
86