Sundance Technology
ST201
PRELIMINARY draft 2
CONFIGCOMMAND
Class | PCI Configuration Registers, Configuration |
Base Address | PCI device configuration header start |
Address Offset | 0x04 |
Access Mode | Read/Write |
Width | 16 bits |
This register provides control over the adapter’s ability to generate and respond to PCI cycles. When a zero is written to this register, the adapter is logically disconnected from the PCI bus, except for configura- tion cycles.
BIT
0
1
2
3
4
5
6
7
8
15..9
BIT NAME
IoSpace
MemorySpace
BusMaster
Reserved
MWlEnable
Reserved
ParityErrorRe- sponse
Reserved
SERREnable
Reserved
BIT DESCRIPTION
Setting this bit allows the adapter to respond to I/O space accesses (if the adapter is in the D0 power state).
Setting this bit along with AddressDecodeEnable in ExpRomBaseAd- dress allows the adapter to decode accesses to its Expansion ROM, if one is installed, and if the adapter is in the D0 power state.
Setting this bit allows adapters with bus master capability to initiate bus master cycles (if the adapter is in the D0 power state).
Reserved for future use. Should be set to 0.
Memory Write and Invalidate Enable. Setting this bit allows the adapter to generate the MWI command.
Reserved for future use. Should be set to 0.
This bit controls how the adapter responds to parity errors. Setting this bit causes the adapter to take its normal action upon detecting a parity error. Clearing this bit causes the adapter to ignore parity errors. This bit is cleared upon system reset.
Reserved for future use. Should be set to 0.
This bit is the enable bit for the SERRN pin driver. A value of zero dis- ables the SERRN driver.
Reserved for future use. Should be set to 0.
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