Sundance Spas ST201 manual Configstatus

Sundance Technology

ST201

PRELIMINARY draft 2

CONFIGSTATUS
Class	PCI Configuration Registers, Configuration
Base Address	PCI device configuration header start
Address Offset	0x06
Access Mode	Read/Write
Width	16 bits

This register is used to record status information for PCI bus events. Read/write bits in the register can only be reset, not set, by writing to this register. Bits are reset by writing a one to that bit position.

BIT

3..0

4

6..5

7

8

10..9

11

12

13

14

15

BIT NAME

Reserved

Capabilities

Reserved

FastBackToBack

DataParityRe- ported

DevselTiming

SignaledTargetA- bort

ReceivedTargetA- bort

ReceivedMaster- Abort

SignaledSystemEr- ror

DetectedParityEr- ror

BIT DESCRIPTION

Reserved for future use. Should be set to 0.

This read-only bit is always set, indicating the existence of a list of extended capabilities registers. The CapPtr register points to the start of the list.

Reserved for future use. Should be set to 0.

This read-only bit, when set, indicates that the adapter, as a Target, supports fast back-to-back transactions as defined by the criteria in the section 3.4.2 of the PCI specification.

The adapter sets this bit when, as a master, it detects the PERRN sig- nal asserted, and the ParityErrorResponse bit is set in the ConfigCom- mand register.

This read-only field is used to encode the slowest time with which the adapter asserts the DEVSELN signal. ST201-based adapters return 01b, indicating that they support “medium”speed DEVSELN assertion.

The adapter sets this bit when it terminates a bus transaction with tar- get-abort.

The adapter sets this bit when, operating as a bus master, its bus transaction is terminated with target-abort.

The adapter sets this bit when, operating as a bus master, its bus transaction is terminated with master-abort.

This bit is set whenever the adapter asserts SERRN.

The adapter sets this bit when it detects a parity error, regardless of whether parity error handling is enabled.

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