Sundance Spas ST201 manual Power Management

Sundance Technology

ST201

PRELIMINARY draft 2

disable the use of MWI and MRL. MWIDisable and MRLDisable are cleared by default, enabling MWI and MRL.

The ST201 provides a set of registers that control the PCI burst behavior. These registers allow a trade-off to be made between PCI bus efficiency and under run/overrun frequency. Arbitration logic within the PCI Bus Interface block accepts bus requests from the TxDMA Logic and RxDMA Logic. The TxDMA Logic uses the TxDMABurstThresh register, as described in the TxDMA Logic section, to delay the bus request until there is enough free space in the TxFIFO for a long, efficient burst. The TxDMA Logic can also make an urgent bus request as described in the TxDMA Logic section, where burst efficiency is sacrificed in favor of avoiding a TxFIFO under run condition.

The RxDMA process is described in the RxDMA Logic section. Typically, RxDMA requests will be forwarded to the Arbiter, however RxDMA Urgent Requests are also possible in order to prevent receive overruns. The Arbiter services the four requests in the fixed priority order as described in the PCI Bus Interface section.

POWER MANAGEMENT

The ST201 supports operating system directed power management according to the ACPI specifi- cation. Power management registers in the PCI configuration space, as defined by the PCI Bus Power Management Interface specification, Revi- sion 1.0 are described in the Registers and Data Structures section.

The ST201 supports several power management states. The PowerState field in the PowerMgmtCtrl register determines ST201’s current power state. The power states are defined as follows:

•D0 Uninitialized (power state 0) is entered as a result of hardware reset, or after a transition from D3 Hot to D0. This state is the same as D0 Active except that the PCI configuration registers are uninitialized. In this state, the ST201 responds to PCI configuration cycles only.

•D0 Active (power state 0) is the normal opera- tional power state for the ST201. In this state, the PCI configuration registers have been ini- tialized by the system, including the IoSpace, MemorySpace, and BusMaster bits in Config- Command, so the ST201 is able to respond to PCI I/O, memory and configuration cycles and can operate as a PCI master. The ST201 can- not signal wake (PMEN) from the D0 state.

•D1 (power state 1) is a “light-sleep”state. The

ST201 optionally supports this state deter- mined by the D1Support bit in the ConfigParm word in EEPROM. The D1 state allows transi- tion back to D0 with no delay. In this state, the ST201 responds to PCI configuration accesses, to allow the system to change the power state. In D1 the ST201 does not respond to any PCI I/O or memory accesses. The ST201’s function in the D1 state is to rec- ognize wake events and link state events and pass them on to the system by asserting the PMEN signal on the PCI bus.

•D2 (power state 2) is a partial power-down state. The ST201 optionally supports this state deter- mined by the D2Support bit in the ConfigParm word in EEPROM. D2 allows a faster transition back to D0 than is possible from the D3 state.

In this state, the ST201 responds to PCI con- figuration accesses, to allow the system to change the power state. In D2 the ST201 does not respond to any PCI I/O or memory accesses. The ST201’s function in the D2 state is to recognize wake events and link state events and pass them on to the system by asserting the PMEN signal on the PCI bus.

•D3 Hot (power state 3) is the full power-down state for the ST201. In D3 Hot, the ST201 loses all PCI configuration information except for the value in PowerState. In this state, the ST201 responds to PCI configuration accesses, to allow the system to change the power state back to D0 Uninitialized. In D3 hot, the ST201 does not respond to any PCI I/O or memory accesses. The ST201’s main respon- sibility in the D3 Hot state is to recognize wake events and link state events and signal those to the system by asserting the PMEN signal on the PCI bus.

•D3 Cold (power state undefined) is the power-off state for the ST201. The ST201 does not func- tion in this state. When power is restored, the system guarantees the assertion of hardware reset, which puts the ST201 into the D0 Unini- tialized state.

The ST201 can generate wake events to the sys- tem as a result of Wake Packet reception, Magic Packet reception, or due to a change in the link sta- tus. The WakeEvent register gives the host system control over which of these events are passed to the system. Wake events are signaled over the PCI bus using the PMEN pin.

A Wake Packet event is controlled by the WakePk- tEnable bit in WakeEvent register. WakePktEnable has no effect when ST201 is in the D0 power state, as the wake process can only take place in states

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