Sundance Technology
ST201
PRELIMINARY draft 2
LATENCYTIMER |
|
Class | PCI Configuration Registers, Configuration |
Base Address | PCI device configuration header start |
Address Offset | 0x0d |
Access Mode | Read/Write |
Width | 8 bits |
This register specifies, in units of PCI bus clocks, the value of the latency timer for bus master operations. The host system writes a value into LatencyTimer, which determines how long the ST201 may hold the bus in the presence of other bus requestors. Whenever the ST201 asserts FRAMEN, the latency timer is started. When the timer count expires, the ST201 must relinquish the bus as soon as its GNTN signal has been negated. The granularity of the timer is 8 bus clocks.
BIT
2..0
7..3
BIT NAME
Reserved
LatencyTimer
BIT DESCRIPTION
Reserved for future use. Should be set to 0.
Indicates, in increments of 8 bus clocks, the length of time which the ST201 may hold the PCI bus in the presence of other bus requestors.
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