Usage Guidelines | Handling SRQ and the IEEE488.2 Status Structures |
Responding to SRQ events
The SRQ event of the IEEE488.2 bus is the summary of the entire Status Structure of the XMP 2600.
The following paragraphs will show how to traverse the Status Structure tree in order to find the cause of the generated SRQ.
This explanation will, also, show how to setup the programmable elements of Status Structure in order to be notified only on events of interest.
The (main) status byte
The SRQ event is generated in response to bits of the Status Byte being set (a positive transition).
Each time a bit of the Status Byte is being set (changing from 0 to 1) the Status Byte is being ANDed with the Service Request Enable Register. If the result of the AND operation has any bits set to 1 – an SRQ will be generated. In other words – the SRQ event (or flag) is the summary of the Status Byte and the Service Request Enable Register is the “Event Enable Register”.
Thus, the first response to an SRQ event is to read the Status Byte. This can be achieved in two fashions: performing a serial poll or issuing the *STB? Query.
Once we have got the value of the Status Byte, we can investigate the cause of the SRQ event.
The Status Byte summarizes the following Status Structures: ESB - XMP’s main controller events
MAV - Output Message Queue (Message AVailable). COM TO – Remote Communications Time Out.
PRIM ERR - XMP’s Primary Engine (main converter) faults. SRQ IS - Power Modules.
Whenever one of these bits is set, the corresponding higher level of the Status Structure should be probed.
Main controller events
This part of the Status Structure is made out of an Event Register and its corresponding Event Enable Register. The summary of this pair of registers appears in the Status Byte in the form of the ESB bit.
The main controller’s Event Register (also called the Standard Event Status Register) holds the Power On, Error and OPC events. The register is read using the *ESR? Query. The last known error code is read using the ERR? Query.
The OPC event (OPeration Complete) occurs when the *OPC command follows a lengthy operation (e.g. a change in the output voltage of a Power Module – VSET command).
The PON event occurs when the XMP 2600 is powered up.
Output message Queue
The MAV (Message AVailable) bit of the Status Register is the only element of this part of the Status Structure.
The bit is set to 1 whenever the Output Queue holds a response to a query.
This enables the software of the controlling computer to work with the XMP 2600 asynchronously.
XMP 2600 Programming Manual rev. 1.1 | 13 |
