Texas Instruments TMS320DM646x manuals

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Texas Instruments TMS320DM646x Manual

135 pages989.86 Kb

3Contents
- Preface
10Read This First
- 1 Introduction
- 1.1 Purpose of the Peripheral 1.2 Features
- User's Guide
12Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
- 131.3 Functional Block Diagram
- 141.4 Industry Standard(s) Compliance Statement
- 2 Architecture 2.1 Clock Control
- 152.2 Memory Map
- 2.3 Signal Descriptions
  - 16Table 1. EMAC and MDIO Signals for MII Interface
  - 172.3.2 Gigabit Media Independent Interface (GMII) Connections
  - Table 2. EMAC and MDIO Signals for GMII Interface
  - 18Table 2. EMAC and MDIO Signals for GMII Interface (continued)
- 192.4 Ethernet Protocol Overview
- 202.5 Programming Interface
  - 21Table 4. Basic Descriptor Description
  - Figure 6. Typical Descriptor Linked List
  - 242.5.4 Transmit Buffer Descriptor Format
  - Example 1. Transmit Buffer Descriptor in C Structure Format
- 312.6 EMAC Control Module
- 342.7 MDIO Module
- 382.8 EMAC Module
- 412.9 Media Independent Interface (MII)
- 452.10 Packet Receive Operation
- 502.11 Packet Transmit Operation
- 2.12 Receive and Transmit Latency
- 512.13 Transfer Node Priority
- 2.14 Reset Considerations
- 522.15 Initialization
  - 53Example 4. EMAC Control Module Initialization Code
- 562.16 Interrupt Support
- 602.17 Power Management
- 2.18 Emulation Considerations
- 613 EMAC Control Module Registers
- 3.1 EMAC Control Module Identification and Version Register (CMIDVER)
  - Table 10. EMAC Control Module Identification and Version Register (CMIDVER)Field Descriptions
- 623.2 EMAC Control Module Software Reset Register (CMSOFTRESET)
- 3.3 EMAC Control Module Emulation Control Register (CMEMCONTROL)
  - Table 11. EMAC Control Module Software Reset Register (CMSOFTRESET) Field Descriptions
  - Table 12. EMAC Control Module Emulation Control Register (CMEMCONTROL)Field Descriptions
- 633.4 EMAC Control Module Interrupt Control Register (CMINTCTRL)
  - Table 13. EMAC Control Module Interrupt Control Register (CMINTCTRL)Field Descriptions
- 643.5 EMAC Control Module Receive Threshold Interrupt Enable Register
- 3.6 EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
- (CMRXTHRESHINTEN)
  - Table 15. EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)Field Descriptions
- 653.7 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)
- 663.8 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN)
- 673.9 EMAC Control Module Receive Threshold Interrupt Status Register
- 3.10 EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
- (CMRXTHRESHINTSTAT)
  - Table 19. EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)Field Descriptions
- 683.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)
- 693.12 EMAC Control Module Miscellaneous Interrupt Status Register (EWMISCSTAT)
- 703.13 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX)
- 3.14 EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX)
- 714 MDIO Registers
- 4.1 MDIO Version Register (VERSION)
  - Table 25. MDIO Version Register (VERSION) Field Descriptions
- 724.2 MDIO Control Register (CONTROL)
  - Table 26. MDIO Control Register (CONTROL) Field Descriptions
- 734.3 PHY Acknowledge Status Register (ALIVE)
- 4.4 PHY Link Status Register (LINK)
- 744.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
- 754.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
- 764.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
- 774.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
- 784.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
- 794.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
- 804.11 MDIO User Access Register 0 (USERACCESS0)
  - Table 35. MDIO User Access Register 0 (USERACCESS0) Field Descriptions
- 814.12 MDIO User PHY Select Register 0 (USERPHYSEL0)
  - Table 36. MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions
- 824.13 MDIO User Access Register 1 (USERACCESS1)
  - Table 37. MDIO User Access Register 1 (USERACCESS1) Field Descriptions
- 834.14 MDIO User PHY Select Register 1 (USERPHYSEL1)
  - Table 38. MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions
- 845 Ethernet Media Access Controller (EMAC) Registers
  - 86Table 39. Ethernet Media Access Controller (EMAC) Registers (continued)
- 875.1 Transmit Identification and Version Register (TXIDVER)
- 5.2 Transmit Control Register (TXCONTROL)
  - Table 40. Transmit Identification and Version Register (TXIDVER) Field Descriptions
  - Table 41. Transmit Control Register (TXCONTROL) Field Descriptions
- 885.3 Transmit Teardown Register (TXTEARDOWN)
  - Table 42. Transmit Teardown Register (TXTEARDOWN) Field Descriptions
- 895.4 Receive Identification and Version Register (RXIDVER)
- 5.5 Receive Control Register (RXCONTROL)
  - Table 43. Receive Identification and Version Register (RXIDVER) Field Descriptions
  - Table 44. Receive Control Register (RXCONTROL) Field Descriptions
- 905.6 Receive Teardown Register (RXTEARDOWN)
  - Table 45. Receive Teardown Register (RXTEARDOWN) Field Descriptions
- 915.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
  - Table 46. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
- 925.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
  - Table 47. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
- 935.9 Transmit Interrupt Mask Set Register (TXINTMASKSET)
  - Table 48. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
- 945.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
  - Table 49. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
- 955.11 MAC Input Vector Register (MACINVECTOR)
- 5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR)
  - Table 50. MAC Input Vector Register (MACINVECTOR) Field Descriptions
  - Table 51. MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions
- 965.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
  - Table 52. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
- 975.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
  - Table 53. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
- 985.15 Receive Interrupt Mask Set Register (RXINTMASKSET)
  - Table 54. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
- 995.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
  - Table 55. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
- 1005.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
- 5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
- 1015.19 MAC Interrupt Mask Set Register (MACINTMASKSET)
- 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
- 1025.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
- 1055.22 Receive Unicast Enable Set Register (RXUNICASTSET)
  - Table 61. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
- 1065.23 Receive Unicast Clear Register (RXUNICASTCLEAR)
  - Table 62. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
- 1075.24 Receive Maximum Length Register (RXMAXLEN)
- 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET)
- 1085.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
- 5.27 Receive Channel 0-7 Flow Control Threshold Register (RX nFLOWTHRESH)
- 1095.28 Receive Channel 0-7 Free Buffer Count Register (RX nFREEBUFFER)
- 1105.29 MAC Control Register (MACCONTROL)
  - Table 68. MAC Control Register (MACCONTROL) Field Descriptions
  - 111Table 68. MAC Control Register (MACCONTROL) Field Descriptions (continued)
- 1125.30 MAC Status Register (MACSTATUS)
  - Table 69. MAC Status Register (MACSTATUS) Field Descriptions
  - 113Table 69. MAC Status Register (MACSTATUS) Field Descriptions (continued)
- 1145.31 Emulation Control Register (EMCONTROL)
- 5.32 FIFO Control Register (FIFOCONTROL)
- 1155.33 MAC Configuration Register (MACCONFIG)
- 5.34 Soft Reset Register (SOFTRESET)
  - Table 72. MAC Configuration Register (MACCONFIG) Field Descriptions
  - Table 73. Soft Reset Register (SOFTRESET) Field Descriptions
- 1165.35 MAC Source Address Low Bytes Register (MACSRCADDRLO)
- 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI)
- 1175.37 MAC Hash Address Register 1 (MACHASH1)
- 5.38 MAC Hash Address Register 2 (MACHASH2)
- 1185.39 Back Off Test Register (BOFFTEST)
- 5.40 Transmit Pacing Algorithm Test Register (TPACETEST)
- 1195.41 Receive Pause Timer Register (RXPAUSE)
- 5.42 Transmit Pause Timer Register (TXPAUSE)
- 1205.43 MAC Address Low Bytes Register (MACADDRLO)
  - Table 82. MAC Address Low Bytes Register (MACADDRLO) Field Descriptions
- 1215.44 MAC Address High Bytes Register (MACADDRHI)
- 5.45 MAC Index Register (MACINDEX)
- 1225.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TX nHDP)
- 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RX nHDP)
- 1235.48 Transmit Channel 0-7 Completion Pointer Register (TX nCP)
- 5.49 Receive Channel 0-7 Completion Pointer Register (RX nCP)
- 1245.50 Network Statistics Registers
- 133Appendix A Glossary
  - 135IMPORTANT NOTICE

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