Texas Instruments TMS320DM646x manual Back Off Test Register BOFFTEST

Models: TMS320DM646x

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5.39 Back Off Test Register (BOFFTEST)

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Ethernet Media Access Controller (EMAC) Registers

5.39 Back Off Test Register (BOFFTEST)

The back off test register (BOFFTEST) is shown in Figure 79 and described in Table 78.

Figure 79. Back Off Random Number Generator Test Register (BOFFTEST)

31

 

 

26

25

16

 

Reserved

 

 

 

RNDNUM

 

R-0

 

 

 

R-0

15

12

11

10

9

0

 

COLLCOUNT

Reserved

 

TXBACKOFF

 

R-0

 

R-0

 

R-0

LEGEND: R = Read only; -n= value after reset

Table 78. Back Off Test Register (BOFFTEST) Field Descriptions

Bit

Field

Value

Description

31-26

Reserved

0

Reserved

25-16

RNDNUM

0-3FFh

Backoff random number generator. This field allows the Backoff Random Number Generator to be

 

 

 

read. Reading this field returns the generator's current value. The value is reset to 0 and begins

 

 

 

counting on the clock after the deassertion of reset.

15-12

COLLCOUNT

0-Fh

Collision count. These bits indicate the number of collisions the current frame has experienced.

11-10

Reserved

0

Reserved

9-0

TXBACKOFF

0-3FFh

Backoff count. This field allows the current value of the backoff counter to be observed for test

 

 

 

purposes. This field is loaded automatically according to the backoff algorithm, and is decremented

 

 

 

by one for each slot time after the collision.

5.40 Transmit Pacing Algorithm Test Register (TPACETEST)

The transmit pacing algorithm test register (TPACETEST) is shown in Figure 80 and described in Table 79.

Figure 80. Transmit Pacing Algorithm Test Register (TPACETEST)

31

 

 

16

 

Reserved

 

 

 

R-0

 

 

15

5

4

0

Reserved

 

 

PACEVAL

R-0

 

 

R-0

LEGEND: R = Read only; -n= value after reset

Table 79. Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions

Bit

Field

Value

Description

 

31-5

Reserved

0

Reserved

 

4-0

PACEVAL

0-1Fh

Pacing register current value. A nonzero value in this field indicates that transmit pacing is active. A

 

 

 

transmit frame collision or deferral causes PACEVAL to be loaded with 1Fh (31); good frame

 

 

 

transmissions (with no collisions or deferrals) cause PACEVAL to be decremented down to 0. When

 

 

 

PACEVAL is nonzero, the transmitter delays four Inter Packet Gaps between new frame transmissions

 

 

 

after each successfully transmitted frame that had no deferrals or collisions. If a transmit frame is

 

 

 

deferred or suffers a collision, the IPG time is not stretched to four times the normal value. Transmit

 

 

 

pacing helps reduce capture effects, which improves overall network bandwidth.

118

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

SPRUEQ6–December 2007

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Texas Instruments TMS320DM646x manual Back Off Test Register BOFFTEST, Transmit Pacing Algorithm Test Register TPACETEST