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Ethernet Media Access Controller (EMAC) Registers

5.39 Back Off Test Register (BOFFTEST)

The back off test register (BOFFTEST) is shown in Figure 79 and described in Table 78.

Figure 79. Back Off Random Number Generator Test Register (BOFFTEST)

31

 

 

26

25

16

 

Reserved

 

 

 

RNDNUM

 

R-0

 

 

 

R-0

15

12

11

10

9

0

 

COLLCOUNT

Reserved

 

TXBACKOFF

 

R-0

 

R-0

 

R-0

LEGEND: R = Read only; -n= value after reset

Table 78. Back Off Test Register (BOFFTEST) Field Descriptions

Bit

Field

Value

Description

31-26

Reserved

0

Reserved

25-16

RNDNUM

0-3FFh

Backoff random number generator. This field allows the Backoff Random Number Generator to be

 

 

 

read. Reading this field returns the generator's current value. The value is reset to 0 and begins

 

 

 

counting on the clock after the deassertion of reset.

15-12

COLLCOUNT

0-Fh

Collision count. These bits indicate the number of collisions the current frame has experienced.

11-10

Reserved

0

Reserved

9-0

TXBACKOFF

0-3FFh

Backoff count. This field allows the current value of the backoff counter to be observed for test

 

 

 

purposes. This field is loaded automatically according to the backoff algorithm, and is decremented

 

 

 

by one for each slot time after the collision.

5.40 Transmit Pacing Algorithm Test Register (TPACETEST)

The transmit pacing algorithm test register (TPACETEST) is shown in Figure 80 and described in Table 79.

Figure 80. Transmit Pacing Algorithm Test Register (TPACETEST)

31

 

 

16

 

Reserved

 

 

 

R-0

 

 

15

5

4

0

Reserved

 

 

PACEVAL

R-0

 

 

R-0

LEGEND: R = Read only; -n= value after reset

Table 79. Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions

Bit

Field

Value

Description

 

31-5

Reserved

0

Reserved

 

4-0

PACEVAL

0-1Fh

Pacing register current value. A nonzero value in this field indicates that transmit pacing is active. A

 

 

 

transmit frame collision or deferral causes PACEVAL to be loaded with 1Fh (31); good frame

 

 

 

transmissions (with no collisions or deferrals) cause PACEVAL to be decremented down to 0. When

 

 

 

PACEVAL is nonzero, the transmitter delays four Inter Packet Gaps between new frame transmissions

 

 

 

after each successfully transmitted frame that had no deferrals or collisions. If a transmit frame is

 

 

 

deferred or suffers a collision, the IPG time is not stretched to four times the normal value. Transmit

 

 

 

pacing helps reduce capture effects, which improves overall network bandwidth.

118

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

SPRUEQ6–December 2007

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Texas Instruments TMS320DM646x manual Back Off Test Register Bofftest, Transmit Pacing Algorithm Test Register Tpacetest

TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

At the core of the TMS320DM646x is the versatile DSP architecture, which optimizes performance for digital signal processing tasks. This architecture allows for real-time processing, enabling the devices to handle complex algorithms necessary for image and video compression, thereby meeting the rigorous demands of modern multimedia applications.

One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

The series supports a wide range of video formats and technologies, including HD video encoding and decoding, which accommodates HD resolution content essential for today’s multimedia applications. Furthermore, the TMS320DM646x integrates hardware accelerators for video compression standards such as H.264 and MPEG-4, which significantly reduce the processing burden on the CPU, resulting in lower power consumption and higher efficiency.

Networking capabilities are another significant feature of the TMS320DM646x. With support for Ethernet, the device can handle streaming media applications and connectivity, facilitating the transmission of high-quality audio and video over the internet. This connectivity is crucial for developing robust IPTV and streaming solutions.

Power management is a primary focus in the design of the TMS320DM646x series. The processors are built to operate efficiently with minimal power consumption, making them suitable for portable and battery-operated devices. The low power characteristics do not compromise performance, enabling high computational capabilities while maintaining energy efficiency.

Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.