Manuals
/
Texas Instruments
/
Computer Equipment
/
Computer Hardware
Texas Instruments
TMS320DM646x manual Users Guide, Management Data Input/Output MDIO Module
Models:
TMS320DM646x
1
1
135
135
Download
135 pages
29.86 Kb
1
2
3
4
5
6
7
8
<
>
Error messages
Functional Block Diagram
Ethernet Configuration-MII Connections
Soft Reset Register SOFTRESET Field Descriptions
MDIO User Command Complete Interrupt Unmasked Register USERINTRAW
Host Error Interrupt
Receive Pause Timer Register RXPAUSE
EMAC and MDIO Signals for MII Interface
Power Management
EMAC Control Module Receive Threshold Interrupt Enable Register
Page 1
Image 1
TMS320DM646x DMSoC
Ethernet Media Access Controller (EMAC)/
Management Data Input/Output (MDIO)
Module
User's Guide
Literature Number: SPRUEQ6
December 2007
Page 2
Page 1
Image 1
Page 2
Contents
Users Guide
TMS320DM646x DMSoC Ethernet Media Access Controller EMAC
Management Data Input/Output MDIO Module
Submit Documentation Feedback
SPRUEQ6-December
Contents
PHY Acknowledge Status Register ALIVE
MAC Hash Address Register 1 MACHASH1
List of Figures
List of Figures
Receive Interrupt Mask Set Register RXINTMASKSET
List of Tables
MAC Control Register MACCONTROL Field Descriptions
Soft Reset Register SOFTRESET Field Descriptions
MAC Status Register MACSTATUS Field Descriptions
FIFO Control Register FIFOCONTROL Field Descriptions
Preface
Read This First
About This Manual
Notational Conventions
Read This First
Related Documentation From Texas Instruments
1.2 Features
Users Guide
1 Introduction
1.1 Purpose of the Peripheral
Figure 1. EMAC and MDIO Block Diagram
1.3 Functional Block Diagram
2 Architecture
1.4 Industry Standards Compliance Statement
2.1 Clock Control
2.1.1 MII Clocking
Figure 2. Ethernet Configuration-MII Connections
2.3 Signal Descriptions
2.2 Memory Map
2.3.1 Media Independent Interface MII Connections
Signal
Table 1. EMAC and MDIO Signals for MII Interface
Architecture
Type
Table 2. EMAC and MDIO Signals for GMII Interface
Figure 3. Ethernet Configuration-GMII Connections
2.3.2 Gigabit Media Independent Interface GMII Connections
MTCLK GMTCLK RFTCLK MTXD7−0 MTXEN MCOL MCRS MRCLK MRXD7−0 MRXDV MRXER
Signal
Table 2. EMAC and MDIO Signals for GMII Interface continued
Architecture
Type
2.4.1 Ethernet Frame Format
2.4 Ethernet Protocol Overview
Figure 4. Ethernet Frame Format
Table 3. Ethernet Frame Description
2.5 Programming Interface
2.4.2 Ethernet’s Multiple Access Protocol
2.5.1 Packet Buffer Descriptors
Figure 5. Basic Descriptor Format
Figure 6. Typical Descriptor Linked List
Table 4. Basic Descriptor Description
2.5.2 Transmit and Receive Descriptor Queues
2.5.3 Transmit and Receive EMAC Interrupts
Figure 7. Transmit Buffer Descriptor Format
2.5.4 Transmit Buffer Descriptor Format
Example 1. Transmit Buffer Descriptor in C Structure Format
Architecture
2.5.4.2 Buffer Pointer
2.5.4.1 Next Descriptor Pointer
2.5.4.3 Buffer Offset
2.5.4.4 Buffer Length
2.5.4.8 Ownership OWNER Flag
2.5.4.7 End of Packet EOP Flag
2.5.4.9 End of Queue EOQ Flag
2.5.4.10 Teardown Complete TDOWNCMPLT Flag
2.5.5.1 Next Descriptor Pointer
2.5.5 Receive Buffer Descriptor Format
2.5.5.2 Buffer Pointer
Figure 8. Receive Buffer Descriptor Format
2.5.5.3 Buffer Offset
Example 2. Receive Buffer Descriptor in C Structure Format
2.5.5.5 Packet Length
2.5.5.4 Buffer Length
2.5.5.6 Start of Packet SOP Flag
2.5.5.7 End of Packet EOP Flag
2.5.5.19 Alignment Error ALIGNERROR Flag
2.5.5.18 Code Error CODEERROR Flag
2.5.5.20 CRC Error CRCERROR Flag
2.5.5.10 Teardown Complete TDOWNCMPLT Flag
2.6 EMAC Control Module
Figure 9. EMAC Control Module Block Diagram
2.5.5.21 No Match NOMATCH Flag
2.6.1 Internal Memory
Table 5. EMAC Control Module Interrupts
2.6.3 Interrupt Control
2.6.3.1 Transmit Pulse Interrupt
2.6.3.2 Receive Pulse Interrupt
2.6.3.4 Miscellaneous Pulse Interrupt
2.6.3.3 Receive Threshold Pulse Interrupt
2.6.4 Interrupt Pacing
2.7 MDIO Module
Figure 10. MDIO Module Block Diagram
2.7.1 MDIO Module Components
2.7.1.1 MDIO Clock Generator
2.7.1.2 Global PHY Detection and Link State Monitoring
2.7.1.4 PHY Register User Access
2.7.1.3 Active PHY Monitoring
2.7.2 MDIO Module Operational Overview
2.7.2.2 Writing Data To a PHY Register
2.7.2.1 Initializing the MDIO Module
2.7.2.3 Reading Data From a PHY Register
Example 3. MDIO Register Access Macros
2.7.2.4 Example of MDIO Register Access Code
2.8 EMAC Module
Figure 11. EMAC Module Block Diagram
2.8.1 EMAC Module Components
2.8.1.1 Receive DMA Engine
2.8.1.3 MAC Receiver
2.8.1.12 Clock and Reset Logic
2.8.1.4 Receive Address
2.8.1.5 Transmit DMA Engine
2.8.2 EMAC Module Operational Overview
2.9.1 Data Reception
2.9 Media Independent Interface MII
2.9.1.1 Receive Control
2.9.1.2 Receive Inter-Frame Interval
2.9.1.3.2 IEEE 802.3x-Based Receive Buffer Flow Control
2.9.1.3.1 Collision-Based Receive Buffer Flow Control
2.9.2.1 Transmit Control
2.9.2 Data Transmission
2.9.2.2 CRC Insertion
2.9.2.3 Adaptive Performance Optimization APO
2.9.2.7 Speed, Duplex, and Pause Frame Support
2.9.2.6 Transmit Flow Control
2.10 Packet Receive Operation
2.10.1 Receive DMA Host Configuration
2.10.2 Receive Channel Enabling
2.10.4 Hardware Receive QOS Support
2.10.3 Receive Address Matching
2.10.5 Host Free Buffer Tracking
2.10.7 Receive Frame Classification
2.10.6 Receive Channel Teardown
Table 6. Receive Frame Treatment Summary
2.10.8 Promiscuous Receive Mode
RXCAFEN
RXCEFEN
2.10.9 Receive Overrun
Table 6. Receive Frame Treatment Summary continued
Table 7. Middle of Frame Overrun Treatment
2.11 Packet Transmit Operation
2.11.1 Transmit DMA Host Configuration
2.12 Receive and Transmit Latency
2.11.2 Transmit Channel Teardown
2.14.1 Software Reset Considerations
2.14 Reset Considerations
2.13 Transfer Node Priority
2.15 Initialization
2.14.2 Hardware Reset Considerations
2.15.1 Enabling the EMAC/MDIO Peripheral
2.15.2 EMAC Control Module Initialization
Architecture
Example 4. EMAC Control Module Initialization Code
Submit Documentation Feedback
Example 5. MDIO Module Initialization Code
2.15.3 MDIO Module Initialization
2.15.4 EMAC Module Initialization
2.16 Interrupt Support
Figure 12. EMAC Control Module Interrupt Logic Diagram
2.16.1 EMAC Module Interrupt Events and Requests
2.16.1.1 Receive Threshold Interrupts
2.16.1.3 Receive Packet Completion Interrupts
2.16.1.2 Transmit Packet Completion Interrupts
2.16.1.4 Statistics Interrupt
2.16.1.5 Host Error Interrupt
2.16.2 MDIO Module Interrupt Events and Requests
2.16.2.2 User Access Completion Interrupt
2.16.2.1 Link Change Interrupt
2.16.3 Proper Interrupt Processing
2.18 Emulation Considerations
2.17 Power Management
Table 8. Emulation Control
3.1 EMAC Control Module Identification and Version Register CMIDVER
3 EMAC Control Module Registers
Table 9. EMAC Control Module Registers
Field Descriptions
Figure 14. EMAC Control Module Software Reset Register CMSOFTRESET
3.2 EMAC Control Module Software Reset Register CMSOFTRESET
3.3 EMAC Control Module Emulation Control Register CMEMCONTROL
Figure 15. EMAC Control Module Emulation Control Register CMEMCONTROL
Figure 16. EMAC Control Module Interrupt Control Register CMINTCTRL
3.4 EMAC Control Module Interrupt Control Register CMINTCTRL
Table 13. EMAC Control Module Interrupt Control Register CMINTCTRL
Field Descriptions
3.6 EMAC Control Module Receive Interrupt Enable Register CMRXINTEN
3.5 EMAC Control Module Receive Threshold Interrupt Enable Register
CMRXTHRESHINTEN
CMRXTHRESHINTEN
Field Descriptions
3.7 EMAC Control Module Transmit Interrupt Enable Register CMTXINTEN
Field Descriptions
CMRXTHRESHINTSTAT
3.9 EMAC Control Module Receive Threshold Interrupt Status Register
CMRXTHRESHINTSTAT
CMRXTHRESHINTSTAT Field Descriptions
Field Descriptions
Field Descriptions
3.13 EMAC Control Module Receive Interrupts per Millisecond Register CMRXINTMAX
4.1 MDIO Version Register VERSION
4 MDIO Registers
Table 24. Management Data Input/Output MDIO Registers
Figure 27. MDIO Version Register VERSION
Figure 28. MDIO Control Register CONTROL
4.2 MDIO Control Register CONTROL
Table 26. MDIO Control Register CONTROL Field Descriptions
MDIO Registers
4.4 PHY Link Status Register LINK
4.3 PHY Acknowledge Status Register ALIVE
Figure 29. PHY Acknowledge Status Register ALIVE
Table 27. PHY Acknowledge Status Register ALIVE Field Descriptions
Field Descriptions
4.5 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAW
Field Descriptions
4.6 MDIO Link Status Change Interrupt Masked Register LINKINTMASKED
Field Descriptions
4.7 MDIO User Command Complete Interrupt Unmasked Register USERINTRAW
Field Descriptions
Field Descriptions
Figure 36 and described in Table
Figure 36. MDIO User Command Complete Interrupt Mask Clear Register
USERINTMASKCLEAR
Field Descriptions
Figure 37. MDIO User Access Register 0 USERACCESS0
4.11 MDIO User Access Register 0 USERACCESS0
Table 35. MDIO User Access Register 0 USERACCESS0 Field Descriptions
MDIO Registers
Figure 38. MDIO User PHY Select Register 0 USERPHYSEL0
4.12 MDIO User PHY Select Register 0 USERPHYSEL0
MDIO Registers
Field
Figure 39. MDIO User Access Register 1 USERACCESS1
4.13 MDIO User Access Register 1 USERACCESS1
Table 37. MDIO User Access Register 1 USERACCESS1 Field Descriptions
MDIO Registers
Figure 40. MDIO User PHY Select Register 1 USERPHYSEL1
4.14 MDIO User PHY Select Register 1 USERPHYSEL1
MDIO Registers
Field
Table 39. Ethernet Media Access Controller EMAC Registers
5 Ethernet Media Access Controller EMAC Registers
Ethernet Media Access Controller EMAC Registers
Acronym
Ethernet Media Access Controller EMAC Registers
Table 39. Ethernet Media Access Controller EMAC Registers continued
Offset
Acronym
Ethernet Media Access Controller EMAC Registers
Table 39. Ethernet Media Access Controller EMAC Registers continued
Offset
Acronym
5.2 Transmit Control Register TXCONTROL
5.1 Transmit Identification and Version Register TXIDVER
Figure 41. Transmit Identification and Version Register TXIDVER
Figure 42. Transmit Control Register TXCONTROL
5.3 Transmit Teardown Register TXTEARDOWN
Ethernet Media Access Controller EMAC Registers
Figure 43. Transmit Teardown Register TXTEARDOWN
Table 42. Transmit Teardown Register TXTEARDOWN Field Descriptions
5.5 Receive Control Register RXCONTROL
5.4 Receive Identification and Version Register RXIDVER
Figure 44. Receive Identification and Version Register RXIDVER
Figure 45. Receive Control Register RXCONTROL
5.6 Receive Teardown Register RXTEARDOWN
Ethernet Media Access Controller EMAC Registers
Figure 46. Receive Teardown Register RXTEARDOWN
Table 45. Receive Teardown Register RXTEARDOWN Field Descriptions
5.7 Transmit Interrupt Status Unmasked Register TXINTSTATRAW
Ethernet Media Access Controller EMAC Registers
Figure 47. Transmit Interrupt Status Unmasked Register TXINTSTATRAW
Field
5.8 Transmit Interrupt Status Masked Register TXINTSTATMASKED
Ethernet Media Access Controller EMAC Registers
Figure 48. Transmit Interrupt Status Masked Register TXINTSTATMASKED
Field
5.9 Transmit Interrupt Mask Set Register TXINTMASKSET
Ethernet Media Access Controller EMAC Registers
Figure 49. Transmit Interrupt Mask Set Register TXINTMASKSET
Field
5.10 Transmit Interrupt Mask Clear Register TXINTMASKCLEAR
Ethernet Media Access Controller EMAC Registers
Figure 50. Transmit Interrupt Mask Clear Register TXINTMASKCLEAR
Field
5.12 MAC End Of Interrupt Vector Register MACEOIVECTOR
5.11 MAC Input Vector Register MACINVECTOR
Figure 51. MAC Input Vector Register MACINVECTOR
Table 50. MAC Input Vector Register MACINVECTOR Field Descriptions
5.13 Receive Interrupt Status Unmasked Register RXINTSTATRAW
Ethernet Media Access Controller EMAC Registers
Figure 53. Receive Interrupt Status Unmasked Register RXINTSTATRAW
Field
5.14 Receive Interrupt Status Masked Register RXINTSTATMASKED
Ethernet Media Access Controller EMAC Registers
Figure 54. Receive Interrupt Status Masked Register RXINTSTATMASKED
Field
5.15 Receive Interrupt Mask Set Register RXINTMASKSET
Ethernet Media Access Controller EMAC Registers
Figure 55. Receive Interrupt Mask Set Register RXINTMASKSET
Field
5.16 Receive Interrupt Mask Clear Register RXINTMASKCLEAR
Ethernet Media Access Controller EMAC Registers
Figure 56. Receive Interrupt Mask Clear Register RXINTMASKCLEAR
Field
5.18 MAC Interrupt Status Masked Register MACINTSTATMASKED
5.17 MAC Interrupt Status Unmasked Register MACINTSTATRAW
Figure 57. MAC Interrupt Status Unmasked Register MACINTSTATRAW
Figure 58. MAC Interrupt Status Masked Register MACINTSTATMASKED
5.20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR
5.19 MAC Interrupt Mask Set Register MACINTMASKSET
Figure 59. MAC Interrupt Mask Set Register MACINTMASKSET
Figure 60. MAC Interrupt Mask Clear Register MACINTMASKCLEAR
Field Descriptions
Field Descriptions continued
Ethernet Media Access Controller EMAC Registers
Field
Value
Field Descriptions continued
Ethernet Media Access Controller EMAC Registers
Field
Value
Figure 62. Receive Unicast Enable Set Register RXUNICASTSET
5.22 Receive Unicast Enable Set Register RXUNICASTSET
Ethernet Media Access Controller EMAC Registers
Field
5.23 Receive Unicast Clear Register RXUNICASTCLEAR
Ethernet Media Access Controller EMAC Registers
Figure 63. Receive Unicast Clear Register RXUNICASTCLEAR
Field
5.25 Receive Buffer Offset Register RXBUFFEROFFSET
5.24 Receive Maximum Length Register RXMAXLEN
Figure 64. Receive Maximum Length Register RXMAXLEN
Table 63. Receive Maximum Length Register RXMAXLEN Field Descriptions
Field Descriptions
Field Descriptions
described in Table
5.28 Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER
5.29 MAC Control Register MACCONTROL
Ethernet Media Access Controller EMAC Registers
Figure 69. MAC Control Register MACCONTROL
Table 68. MAC Control Register MACCONTROL Field Descriptions
Description
Field
Submit Documentation Feedback
Value
5.30 MAC Status Register MACSTATUS
Ethernet Media Access Controller EMAC Registers
Figure 70. MAC Status Register MACSTATUS
Table 69. MAC Status Register MACSTATUS Field Descriptions
Field
Table 69. MAC Status Register MACSTATUS Field Descriptions continued
Value
Description
5.32 FIFO Control Register FIFOCONTROL
5.31 Emulation Control Register EMCONTROL
Figure 71. Emulation Control Register EMCONTROL
Table 70. Emulation Control Register EMCONTROL Field Descriptions
5.34 Soft Reset Register SOFTRESET
5.33 MAC Configuration Register MACCONFIG
Figure 73. MAC Configuration Register MACCONFIG
Table 72. MAC Configuration Register MACCONFIG Field Descriptions
5.36 MAC Source Address High Bytes Register MACSRCADDRHI
5.35 MAC Source Address Low Bytes Register MACSRCADDRLO
Figure 75. MAC Source Address Low Bytes Register MACSRCADDRLO
Figure 76. MAC Source Address High Bytes Register MACSRCADDRHI
5.38 MAC Hash Address Register 2 MACHASH2
5.37 MAC Hash Address Register 1 MACHASH1
Figure 77. MAC Hash Address Register 1 MACHASH1
Table 76. MAC Hash Address Register 1 MACHASH1 Field Descriptions
5.40 Transmit Pacing Algorithm Test Register TPACETEST
5.39 Back Off Test Register BOFFTEST
Figure 79. Back Off Random Number Generator Test Register BOFFTEST
Table 78. Back Off Test Register BOFFTEST Field Descriptions
5.42 Transmit Pause Timer Register TXPAUSE
5.41 Receive Pause Timer Register RXPAUSE
Figure 81. Receive Pause Timer Register RXPAUSE
Table 80. Receive Pause Timer Register RXPAUSE Field Descriptions
5.43 MAC Address Low Bytes Register MACADDRLO
Ethernet Media Access Controller EMAC Registers
Figure 83. MAC Address Low Bytes Register MACADDRLO
Table 82. MAC Address Low Bytes Register MACADDRLO Field Descriptions
5.45 MAC Index Register MACINDEX
5.44 MAC Address High Bytes Register MACADDRHI
Figure 84. MAC Address High Bytes Register MACADDRHI
Figure 85. MAC Index Register MACINDEX
5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register RXnHDP
5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register TXnHDP
Field Descriptions
Field Descriptions
5.49 Receive Channel 0-7 Completion Pointer Register RXnCP
5.48 Transmit Channel 0-7 Completion Pointer Register TXnCP
Figure 88. Transmit Channel n Completion Pointer Register TX nCP
Figure 89. Receive Channel n Completion Pointer Register RX nCP
Figure 90. Statistics Register
5.50 Network Statistics Registers
5.50.1 Good Receive Frames Register RXGOODFRAMES
5.50.2 Broadcast Receive Frames Register RXBCASTFRAMES
5.50.6 Receive Alignment/Code Errors Register RXALIGNCODEERRORS
5.50.5 Receive CRC Errors Register RXCRCERRORS
5.50.4 Pause Receive Frames Register RXPAUSEFRAMES
5.50.7 Receive Oversized Frames Register RXOVERSIZED
5.50.9 Receive Undersized Frames Register RXUNDERSIZED
5.50.8 Receive Jabber Frames Register RXJABBER
5.50.10 Receive Frame Fragments Register RXFRAGMENTS
5.50.11 Filtered Receive Frames Register RXFILTERED
5.50.13 Receive Octet Frames Register RXOCTETS
5.50.12 Receive QOS Filtered Frames Register RXQOSFILTERED
5.50.14 Good Transmit Frames Register TXGOODFRAMES
5.50.15 Broadcast Transmit Frames Register TXBCASTFRAMES
5.50.17 Pause Transmit Frames Register TXPAUSEFRAMES
5.50.16 Multicast Transmit Frames Register TXMCASTFRAMES
5.50.18 Deferred Transmit Frames Register TXDEFERRED
5.50.19 Transmit Collision Frames Register TXCOLLISION
5.50.25 Transmit Carrier Sense Errors Register TXCARRIERSENSE
5.50.24 Transmit Underrun Error Register TXUNDERRUN
5.50.21 Transmit Multiple Collision Frames Register TXMULTICOLL
5.50.22 Transmit Excessive Collision Frames Register TXEXCESSIVECOLL
5.50.27 Transmit and Receive 64 Octet Frames Register FRAME64
5.50.26 Transmit Octet Frames Register TXOCTETS
5.50.33 Network Octet Frames Register NETOCTETS
5.50.36 Receive DMA Overruns Register RXDMAOVERRUNS
Ethernet Media Access Controller EMAC Registers
Appendix A
Appendix A Glossary
Table A-1. Physical Layer Definitions
IMPORTANT NOTICE
power.ti.com
Products
Applications