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Ethernet Media Access Controller (EMAC) Registers
5.44 MAC Address High Bytes Register (MACADDRHI)
The MAC address high bytes register (MACADDRHI) is shown in Figure 84 and described in Table 83.
Figure 84. MAC Address High Bytes Register (MACADDRHI)
31 | 24 | 23 | 16 |
| MACADDR2 |
| MACADDR3 |
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15 | 8 | 7 | 0 |
| MACADDR4 |
| MACADDR5 |
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LEGEND: R/W = Read/Write;
Table 83. MAC Address High Bytes Register (MACADDRHI) Field Descriptions
Bit | Field | Value | Description |
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MACADDR2 | MAC source address bits | |||
MACADDR3 | MAC source address bits | (byte 3) | ||
MACADDR4 | MAC source address bits | (byte 4) | ||
MACADDR5 | MAC source address bits | (byte 5). Bit 40 is the group bit. It is forced to 0 and read as 0. | ||
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| Therefore, only unicast addresses are represented in the address table. |
5.45 MAC Index Register (MACINDEX)
The MAC index register (MACINDEX) is shown in Figure 85 and described in Table 84.
Figure 85. MAC Index Register (MACINDEX)
31 |
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| 16 |
| Reserved |
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15 | 3 | 2 | 0 |
Reserved |
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| MACINDEX |
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LEGEND: R = Read only; R/W = Read/Write;
Table 84. MAC Index Register (MACINDEX) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
MACINDEX | MAC address index. The host must write the index into the RX ADDR RAM in the MACINDEX field, | ||
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| followed by the upper |
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| must be initialized prior to enabling packet reception. |
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | 121 | |
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