Texas Instruments TMS320DM646x manual MAC Address High Bytes Register Macaddrhi, MACADDR2

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Ethernet Media Access Controller (EMAC) Registers

5.44 MAC Address High Bytes Register (MACADDRHI)

The MAC address high bytes register (MACADDRHI) is shown in Figure 84 and described in Table 83.

Figure 84. MAC Address High Bytes Register (MACADDRHI)

31	24	23	16
	MACADDR2		MACADDR3
	R/W-0		R/W-0
15	8	7	0
	MACADDR4		MACADDR5
	R/W-0		R/W-0

LEGEND: R/W = Read/Write; -n= value after reset

Table 83. MAC Address High Bytes Register (MACADDRHI) Field Descriptions

Bit	Field	Value	Description
31-24	MACADDR2	0-FFh	MAC source address bits 23-16 (byte 2)
23-16	MACADDR3	0-FFh	MAC source address bits 31-24	(byte 3)
15-8	MACADDR4	0-FFh	MAC source address bits 39-32	(byte 4)
7-0	MACADDR5	0-FFh	MAC source address bits 47-40	(byte 5). Bit 40 is the group bit. It is forced to 0 and read as 0.
			Therefore, only unicast addresses are represented in the address table.

5.45 MAC Index Register (MACINDEX)

The MAC index register (MACINDEX) is shown in Figure 85 and described in Table 84.

Figure 85. MAC Index Register (MACINDEX)

31			16
	Reserved
	R-0
15	3	2	0
Reserved			MACINDEX
R-0			R/W-0

LEGEND: R = Read only; R/W = Read/Write; -n= value after reset

Table 84. MAC Index Register (MACINDEX) Field Descriptions

Bit	Field	Value	Description
31-3	Reserved	0	Reserved
2-0	MACINDEX	0-7h	MAC address index. The host must write the index into the RX ADDR RAM in the MACINDEX field,
			followed by the upper 32-bits of address, followed by the lower 16-bits of address (with control bits). The
			53-bit indexed RAM location is written when the low location is written. All 32 address RAM locations
			must be initialized prior to enabling packet reception.

SPRUEQ6–December 2007	Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)	121
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