48

Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions

93

49

Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions

94

50

MAC Input Vector Register (MACINVECTOR) Field Descriptions

95

51

MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions

95

52

Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions

96

53

Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions

97

54

Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions

98

55

Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions

99

56

MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions

100

57

MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions

100

58

MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions

101

59

MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions

101

60

Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions

102

61

Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions

105

62

Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions

106

63

Receive Maximum Length Register (RXMAXLEN) Field Descriptions

107

64

Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions

107

65

Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions

108

66

Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions

108

67

Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions

109

68

MAC Control Register (MACCONTROL) Field Descriptions

110

69

MAC Status Register (MACSTATUS) Field Descriptions

112

70

Emulation Control Register (EMCONTROL) Field Descriptions

114

71

FIFO Control Register (FIFOCONTROL) Field Descriptions

114

72

MAC Configuration Register (MACCONFIG) Field Descriptions

115

73

Soft Reset Register (SOFTRESET) Field Descriptions

115

74

MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions

116

75

MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions

116

76

MAC Hash Address Register 1 (MACHASH1) Field Descriptions

117

77

MAC Hash Address Register 2 (MACHASH2) Field Descriptions

117

78

Back Off Test Register (BOFFTEST) Field Descriptions

118

79

Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions

118

80

Receive Pause Timer Register (RXPAUSE) Field Descriptions

119

81

Transmit Pause Timer Register (TXPAUSE) Field Descriptions

119

82

MAC Address Low Bytes Register (MACADDRLO) Field Descriptions

120

83

MAC Address High Bytes Register (MACADDRHI) Field Descriptions

121

84

MAC Index Register (MACINDEX) Field Descriptions

121

85

Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions

122

86

Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions

122

87

Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions

123

88

Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions

123

A-1

Physical Layer Definitions

134

SPRUEQ6–December 2007

List of Tables

9

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Texas Instruments TMS320DM646x manual MAC Control Register Maccontrol Field Descriptions

TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

At the core of the TMS320DM646x is the versatile DSP architecture, which optimizes performance for digital signal processing tasks. This architecture allows for real-time processing, enabling the devices to handle complex algorithms necessary for image and video compression, thereby meeting the rigorous demands of modern multimedia applications.

One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

The series supports a wide range of video formats and technologies, including HD video encoding and decoding, which accommodates HD resolution content essential for today’s multimedia applications. Furthermore, the TMS320DM646x integrates hardware accelerators for video compression standards such as H.264 and MPEG-4, which significantly reduce the processing burden on the CPU, resulting in lower power consumption and higher efficiency.

Networking capabilities are another significant feature of the TMS320DM646x. With support for Ethernet, the device can handle streaming media applications and connectivity, facilitating the transmission of high-quality audio and video over the internet. This connectivity is crucial for developing robust IPTV and streaming solutions.

Power management is a primary focus in the design of the TMS320DM646x series. The processors are built to operate efficiently with minimal power consumption, making them suitable for portable and battery-operated devices. The low power characteristics do not compromise performance, enabling high computational capabilities while maintaining energy efficiency.

Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.