Texas Instruments TMS320DM646x manual MAC Control Register MACCONTROL Field Descriptions

48	Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions	93
49	Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions	94
50	MAC Input Vector Register (MACINVECTOR) Field Descriptions	95
51	MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions	95
52	Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions	96
53	Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions	97
54	Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions	98
55	Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions	99
56	MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions	100
57	MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions	100
58	MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions	101
59	MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions	101
60	Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions	102
61	Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions	105
62	Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions	106
63	Receive Maximum Length Register (RXMAXLEN) Field Descriptions	107
64	Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions	107
65	Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions	108
66	Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions	108
67	Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions	109
68	MAC Control Register (MACCONTROL) Field Descriptions	110
69	MAC Status Register (MACSTATUS) Field Descriptions	112
70	Emulation Control Register (EMCONTROL) Field Descriptions	114
71	FIFO Control Register (FIFOCONTROL) Field Descriptions	114
72	MAC Configuration Register (MACCONFIG) Field Descriptions	115
73	Soft Reset Register (SOFTRESET) Field Descriptions	115
74	MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions	116
75	MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions	116
76	MAC Hash Address Register 1 (MACHASH1) Field Descriptions	117
77	MAC Hash Address Register 2 (MACHASH2) Field Descriptions	117
78	Back Off Test Register (BOFFTEST) Field Descriptions	118
79	Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions	118
80	Receive Pause Timer Register (RXPAUSE) Field Descriptions	119
81	Transmit Pause Timer Register (TXPAUSE) Field Descriptions	119
82	MAC Address Low Bytes Register (MACADDRLO) Field Descriptions	120
83	MAC Address High Bytes Register (MACADDRHI) Field Descriptions	121
84	MAC Index Register (MACINDEX) Field Descriptions	121
85	Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions	122
86	Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions	122
87	Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions	123
88	Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions	123
A-1	Physical Layer Definitions	134

SPRUEQ6–December 2007 List of Tables 9

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