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EMAC Control Module Registers
3.9EMAC Control Module Receive Threshold Interrupt Status Register
(CMRXTHRESHINTSTAT)
The receive threshold interrupt status register (CMRXTHRESHINTSTAT) is shown in Figure 21 and described in Table 18.
Figure 21. EMAC Control Module Receive Threshold Interrupt Status Register
(CMRXTHRESHINTSTAT)
31 |
|
| 16 |
| Reserved |
| |
|
|
| |
15 | 8 | 7 | 0 |
Reserved |
|
| RXTHRESHINTTSTAT |
|
|
LEGEND: R = Read only;
Table 18. EMAC Control Module Receive Threshold Interrupt Status Register
(CMRXTHRESHINTSTAT) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
RXTHRESHINTTSTAT[n] |
| Receive threshold interrupt status. Each bit shows the status of the corresponding |
channel n receive threshold interrupt.
Bit n = 0, channel n receive threshold interrupt is not pending.
Bit n = 1, channel n receive threshold interrupt is pending.
3.10 EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
The receive interrupt status register (CMRXINTSTAT) is shown in Figure 22and described in Table 19.
Figure 22. EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
31 |
|
| 16 |
| Reserved |
| |
|
|
| |
15 | 8 | 7 | 0 |
Reserved |
|
| RXPULSEINTTSTAT |
|
|
LEGEND: R = Read only;
Table 19. EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
RXPULSEINTTSTAT[n] |
| Receive interrupt status. Each bit shows the status of the corresponding channel n receive | |
|
|
| interrupt. |
Bit n = 0, channel n receive interrupt is not pending.
Bit n = 1, channel n receive interrupt is pending.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | 67 | |
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