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Ethernet Media Access Controller (EMAC) Registers

5.50.4Pause Receive Frames Register (RXPAUSEFRAMES)

The total number of IEEE 802.3X pause frames received by the EMAC (whether acted upon or not). A pause frame is defined as having all of the following:

∙Contained any unicast, broadcast, or multicast address

∙Contained the length/type field value 88.08h and the opcode 0001h

∙Was of length 64 to RXMAXLEN bytes inclusive

∙Had no CRC error, alignment error, or code error

∙Pause-frames had been enabled on the EMAC (TXFLOWEN bit is set in MACCONTROL).

The EMAC could have been in either half-duplex or full-duplex mode. See Section 2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic.

5.50.5Receive CRC Errors Register (RXCRCERRORS)

The total number of frames received on the EMAC that experienced a CRC error. A frame with CRC errors is defined as having all of the following:

∙Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode

∙Was of length 64 to RXMAXLEN bytes inclusive

∙Had no alignment or code error

∙Had a CRC error. A CRC error is defined as having all of the following:

–A frame containing an even number of nibbles

–Fails the frame check sequence test

See Section 2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic.

5.50.6Receive Alignment/Code Errors Register (RXALIGNCODEERRORS)

The total number of frames received on the EMAC that experienced an alignment error or code error. Such a frame is defined as having all of the following:

∙Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode

∙Was of length 64 to RXMAXLEN bytes inclusive

∙Had either an alignment error or a code error

–An alignment error is defined as having all of the following:

∙A frame containing an odd number of nibbles

∙Fails the frame check sequence test, if the final nibble is ignored

–A code error is defined as a frame that has been discarded because the EMACs MRXER pin is driven with a one for at least one bit-time's duration at any point during the frame's reception.

Overruns have no effect on this statistic.

CRC alignment or code errors can be calculated by summing receive alignment errors, receive code errors, and receive CRC errors.

5.50.7Receive Oversized Frames Register (RXOVERSIZED)

The total number of oversized frames received on the EMAC. An oversized frame is defined as having all of the following:

∙Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode

∙Was greater than RXMAXLEN in bytes

∙Had no CRC error, alignment error, or code error

SPRUEQ6–December 2007

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

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Texas Instruments TMS320DM646x manual Pause Receive Frames Register Rxpauseframes, Receive CRC Errors Register Rxcrcerrors
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TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

At the core of the TMS320DM646x is the versatile DSP architecture, which optimizes performance for digital signal processing tasks. This architecture allows for real-time processing, enabling the devices to handle complex algorithms necessary for image and video compression, thereby meeting the rigorous demands of modern multimedia applications.

One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

The series supports a wide range of video formats and technologies, including HD video encoding and decoding, which accommodates HD resolution content essential for today’s multimedia applications. Furthermore, the TMS320DM646x integrates hardware accelerators for video compression standards such as H.264 and MPEG-4, which significantly reduce the processing burden on the CPU, resulting in lower power consumption and higher efficiency.

Networking capabilities are another significant feature of the TMS320DM646x. With support for Ethernet, the device can handle streaming media applications and connectivity, facilitating the transmission of high-quality audio and video over the internet. This connectivity is crucial for developing robust IPTV and streaming solutions.

Power management is a primary focus in the design of the TMS320DM646x series. The processors are built to operate efficiently with minimal power consumption, making them suitable for portable and battery-operated devices. The low power characteristics do not compromise performance, enabling high computational capabilities while maintaining energy efficiency.

Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.
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