Texas Instruments TMS320DM646x manual EMAC Control Module, No Match NOMATCH Flag, Internal Memory

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Architecture

2.5.5.21No Match (NOMATCH) Flag

This flag is set by the EMAC in the SOP buffer descriptor, if the received packet did not pass any of the EMAC’s address match criteria and was not discarded because the RXCAFEN bit was set in the RXMBPENABLE. Although the packet is a valid Ethernet data packet, it was only received because the EMAC is in promiscuous mode.

2.6EMAC Control Module

The basic functions of the EMAC control module (Figure 9) are to interface the EMAC and MDIO modules to the rest of the system, and to provide for a local memory space to hold EMAC packet buffer descriptors. Local memory is used to help avoid contention to device memory spaces. Other functions include the bus arbiter, and interrupt control and pacing logic control.

Figure 9. EMAC Control Module Block Diagram

Transmit and Receive DMA Controllers

Configuration bus

EMAC interrupts

MDIO interrupts

Arbiter and	CPU
bus switches

8K byte

descriptor memory

Configuration

registers

Interrupt	4 interrupts
control and
	to ARM
pacing logic

2.6.1Internal Memory

The EMAC control module includes 8K bytes of internal memory. The internal memory block is essential for allowing the EMAC to operate more independently of the CPU. It also prevents memory underflow conditions when the EMAC issues read or write requests to descriptor memory. (Memory accesses to read or write the actual Ethernet packet data are protected by the EMAC's internal FIFOs).

A descriptor is a 16-byte memory structure that holds information about a single Ethernet packet buffer, which may contain a full or partial Ethernet packet. Thus with the 8K memory block provided for descriptor storage, the EMAC module can send and received up to a combined 512 packets before it needs to be serviced by application or driver software.

2.6.2Bus Arbiter

The EMAC control module bus arbiter operates transparently to the rest of the system. It is used:

∙To arbitrate between the CPU and EMAC buses for access to internal descriptor memory.

∙To arbitrate between internal EMAC buses for access to system memory.

SPRUEQ6–December 2007 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 31

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