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Ethernet Media Access Controller (EMAC) Registers
5.29 MAC Control Register (MACCONTROL)
The MAC control register (MACCONTROL) is shown in Figure 69 and described in Table 68.
Figure 69. MAC Control Register (MACCONTROL)
31 |
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| 18 | 17 | 16 |
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| Reserved |
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| GIGFORCE | Reserved |
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15 |
| 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Reserved | RXOFFLENBLOCK | RXOWNERSHIP | RXFIFOFLOWEN | CMDIDLE | Rsvd | TXPTYPE | Reserved | |
7 | 6 | 5 | 4 | 3 |
| 2 | 1 | 0 |
GIG | TXPACE | GMIIEN | TXFLOWEN | RXBUFFERFLOWEN | Rsvd | LOOPBACK | FULLDUPLEX | |
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LEGEND: R = Read only; R/W = Read/Write;
Table 68. MAC Control Register (MACCONTROL) Field Descriptions
Bit | Field | Value | Description |
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Reserved | 0 | Reserved |
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17 | GIGFORCE | Gigabit force mode. This bit is used to force the EMAC into gigabit mode, if the MTCLK input | ||
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| signal has been stopped by the PHY. |
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Reserved | 0 | Reserved |
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14 | RXOFFLENBLOCK |
| Receive offset/length word write block. |
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| 0 | Do not block the DMA writes to the receive buffer descriptor offset/buffer length word. | |
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| 1 | Block all EMAC DMA controller writes to the receive buffer descriptor offset/buffer length | |
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| words during packet processing. When this bit is set, the EMAC will never write the third word | |
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| to any receive buffer descriptor. |
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13 | RXOWNERSHIP |
| Receive ownership write bit value. |
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| 0 | EMAC writes the Receive ownership bit to 0 at the end of packet processing. | |
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| 1 | EMAC writes the Receive ownership bit to 1 at the end of packet processing. If you do not use | |
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| the ownership mechanism, you can set this mode to preclude the necessity of software having | |
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| to set this bit each time the buffer descriptor is used. |
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12 | RXFIFOFLOWEN |
| Receive FIFO flow control enable bit. |
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| 0 | Receive flow control is disabled. | |
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| 1 | Receive flow control is enabled. | |
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| receive FIFO flow control is triggered. |
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11 | CMDIDLE |
| Command Idle bit. |
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| 0 | Idle is not commanded. |
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| 1 | Idle is commanded (read the IDLE bit in the MACSTATUS register). | |
10 | Reserved | 0 | Reserved |
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9 | TXPTYPE |
| Transmit queue priority type. |
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| 0 | The queue uses a | |
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| 1 | The queue uses a | |
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| channel for transmission. |
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8 | Reserved | 0 | Reserved |
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7 | GIG |
| Gigabit mode bit. |
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| 0 | Gigabit mode is disabled; 10/100 mode is in operation. |
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| 1 | Gigabit mode is enabled |
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6 | TXPACE |
| Transmit pacing enable bit. |
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| 0 | Transmit pacing is disabled. |
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| 1 | Transmit pacing is enabled. |
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110 | Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) |
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