Texas Instruments TMS320DM646x manual Receive Frame Treatment Summary continued, Receive Overrun

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					Architecture
	Table 6. Receive Frame Treatment Summary (continued)
Address Match	RXCAFEN	RXCEFEN	RXCMFEN	RXCSFEN	Receive Frame Treatment
1	X	1	1	0	Proper/oversize/jabber/code/align/CRC data and
					control frames transferred to address match
					channel. No undersized/fragment frames are
					transferred.
1	X	1	1	1	All address matching frames with and without
					errors transferred to the address match channel

2.10.9Receive Overrun

The types of receive overrun are:

∙FIFO start of frame overrun (FIFO_SOF)

∙FIFO middle of frame overrun (FIFO_MOF)

∙DMA start of frame overrun (DMA_SOF)

∙DMA middle of frame overrun (DMA_MOF)

The statistics counters used to track these types of receive overrun are:

∙Receive start of frame overruns register (RXSOFOVERRUNS)

∙Receive middle of frame overruns register (RXMOFOVERRUNS)

∙Receive DMA overruns register (RXDMAOVERRUNS)

Start of frame overruns happen when there are no resources available when frame reception begins. Start of frame overruns increment the appropriate overrun statistic(s) and the frame is filtered.

Middle of frame overruns happen when there are some resources to start the frame reception, but the resources run out during frame reception. In normal operation, a frame that overruns after starting the frame reception is filtered and the appropriate statistic(s) are incremented; however, the RXCEFEN bit in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) affects overrun frame treatment. Table 7 shows how the overrun condition is handled for the middle of frame overrun.

Table 7. Middle of Frame Overrun Treatment

Address Match	RXCAFEN	RXCEFEN	Middle of Frame Overrun Treatment
0	0	X	Overrun frame filtered.
0	1	0	Overrun frame filtered.
0	1	1	As much frame data as possible is transferred to the promiscuous channel
			until overrun. The appropriate overrun statistic(s) is incremented and the
			OVERRUN and NOMATCH flags are set in the SOP buffer descriptor. Note
			that the RXMAXLEN number of bytes cannot be reached for an overrun to
			occur (it would be truncated and be a jabber or oversize).
1	X	0	Overrun frame filtered with the appropriate overrun statistic(s) incremented.
1	X	1	As much frame data as possible is transferred to the address match
			channel until overrun. The appropriate overrun statistic(s) is incremented
			and the OVERRUN flag is set in the SOP buffer descriptor. Note that the
			RXMAXLEN number of bytes cannot be reached for an overrun to occur (it
			would be truncated).

SPRUEQ6–December 2007	Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)	49
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