www.ti.com

 

 

 

 

 

Architecture

 

Table 6. Receive Frame Treatment Summary (continued)

Address Match

RXCAFEN

RXCEFEN

RXCMFEN

RXCSFEN

Receive Frame Treatment

1

X

1

1

0

Proper/oversize/jabber/code/align/CRC data and

 

 

 

 

 

control frames transferred to address match

 

 

 

 

 

channel. No undersized/fragment frames are

 

 

 

 

 

transferred.

1

X

1

1

1

All address matching frames with and without

 

 

 

 

 

errors transferred to the address match channel

2.10.9Receive Overrun

The types of receive overrun are:

∙FIFO start of frame overrun (FIFO_SOF)

∙FIFO middle of frame overrun (FIFO_MOF)

∙DMA start of frame overrun (DMA_SOF)

∙DMA middle of frame overrun (DMA_MOF)

The statistics counters used to track these types of receive overrun are:

∙Receive start of frame overruns register (RXSOFOVERRUNS)

∙Receive middle of frame overruns register (RXMOFOVERRUNS)

∙Receive DMA overruns register (RXDMAOVERRUNS)

Start of frame overruns happen when there are no resources available when frame reception begins. Start of frame overruns increment the appropriate overrun statistic(s) and the frame is filtered.

Middle of frame overruns happen when there are some resources to start the frame reception, but the resources run out during frame reception. In normal operation, a frame that overruns after starting the frame reception is filtered and the appropriate statistic(s) are incremented; however, the RXCEFEN bit in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) affects overrun frame treatment. Table 7 shows how the overrun condition is handled for the middle of frame overrun.

Table 7. Middle of Frame Overrun Treatment

Address Match

RXCAFEN

RXCEFEN

Middle of Frame Overrun Treatment

0

0

X

Overrun frame filtered.

0

1

0

Overrun frame filtered.

0

1

1

As much frame data as possible is transferred to the promiscuous channel

 

 

 

until overrun. The appropriate overrun statistic(s) is incremented and the

 

 

 

OVERRUN and NOMATCH flags are set in the SOP buffer descriptor. Note

 

 

 

that the RXMAXLEN number of bytes cannot be reached for an overrun to

 

 

 

occur (it would be truncated and be a jabber or oversize).

1

X

0

Overrun frame filtered with the appropriate overrun statistic(s) incremented.

1

X

1

As much frame data as possible is transferred to the address match

 

 

 

channel until overrun. The appropriate overrun statistic(s) is incremented

 

 

 

and the OVERRUN flag is set in the SOP buffer descriptor. Note that the

 

 

 

RXMAXLEN number of bytes cannot be reached for an overrun to occur (it

 

 

 

would be truncated).

SPRUEQ6–December 2007

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

49

Submit Documentation Feedback

 

 

Page 48 Page 50
Page 49
Image 49
Texas Instruments TMS320DM646x manual Receive Frame Treatment Summary, Receive Overrun, Middle of Frame Overrun Treatment
Page 48 Page 50

TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

At the core of the TMS320DM646x is the versatile DSP architecture, which optimizes performance for digital signal processing tasks. This architecture allows for real-time processing, enabling the devices to handle complex algorithms necessary for image and video compression, thereby meeting the rigorous demands of modern multimedia applications.

One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

The series supports a wide range of video formats and technologies, including HD video encoding and decoding, which accommodates HD resolution content essential for today’s multimedia applications. Furthermore, the TMS320DM646x integrates hardware accelerators for video compression standards such as H.264 and MPEG-4, which significantly reduce the processing burden on the CPU, resulting in lower power consumption and higher efficiency.

Networking capabilities are another significant feature of the TMS320DM646x. With support for Ethernet, the device can handle streaming media applications and connectivity, facilitating the transmission of high-quality audio and video over the internet. This connectivity is crucial for developing robust IPTV and streaming solutions.

Power management is a primary focus in the design of the TMS320DM646x series. The processors are built to operate efficiently with minimal power consumption, making them suitable for portable and battery-operated devices. The low power characteristics do not compromise performance, enabling high computational capabilities while maintaining energy efficiency.

Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.
Top Page Image Contents