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Architecture

 

 

Table 4. Basic Descriptor Description

Word Offset

Field

Field Description

0

Next Descriptor

The next descriptor pointer is used to create a single linked list of descriptors. Each descriptor

 

Pointer

describes a packet or a packet fragment. When a descriptor points to a single buffer packet

 

 

or the first fragment of a packet, the start of packet (SOP) flag is set in the flags field. When a

 

 

descriptor points to a single buffer packet or the last fragment of a packet, the end of packet

 

 

(EOP) flag is set. When a packet is fragmented, each fragment must have its own descriptor

 

 

and appear sequentially in the descriptor linked list.

1

Buffer Pointer

The buffer pointer refers to the actual memory buffer that contains packet data during

 

 

transmit operations, or is an empty buffer ready to receive packet data during receive

 

 

operations.

2

Buffer Offset

The buffer offset is the offset from the start of the packet buffer to the first byte of valid data.

 

 

This field only has meaning when the buffer descriptor points to a buffer that actually contains

 

 

data.

 

Buffer Length

The buffer length is the actual number of valid packet data bytes stored in the buffer. If the

 

 

buffer is empty and waiting to receive data, this field represents the size of the empty buffer.

3

Flags

The flags field contains more information about the buffer, such as, is it the first fragment in a

 

 

packet (SOP), the last fragment in a packet (EOP), or contains an entire contiguous Ethernet

 

 

packet (both SOP and EOP). The flags are described in Section 2.5.4 and Section 2.5.5.

 

Packet Length

The packet length only has meaning for buffers that both contain data and are the start of a

 

 

new packet (SOP). In the case of SOP descriptors, the packet length field contains the length

 

 

of the entire Ethernet packet, regardless if it is contained in a single buffer or fragmented over

 

 

several buffers.

Figure 6. Typical Descriptor Linked List

pNext

pBuffer

 

0

 

60

 

 

 

 

 

 

 

SOP EOP

 

60

 

 

 

 

 

 

pNext

 

 

 

pBuffer

 

 

 

 

 

 

 

 

 

 

 

0

 

512

 

 

 

 

 

 

 

SOP

 

1514

 

 

 

 

 

 

 

 

 

 

 

pNext

 

 

 

 

 

 

 

 

pBuffer

 

 

 

 

 

 

 

 

 

 

 

0

 

502

 

 

 

 

 

 

 

−−−

 

−−−

 

 

 

 

 

 

 

 

 

 

 

 

pNext

 

 

 

 

 

 

 

 

pBuffer

 

 

 

 

 

 

 

 

 

 

 

0

 

500

 

 

 

 

 

 

 

EOP

 

−−−

 

 

 

 

 

 

 

 

 

 

pNext (NULL)

 

 

 

 

pBuffer

 

 

 

 

 

 

 

 

 

 

 

0

 

1514

 

 

 

 

 

 

 

SOP EOP

 

1514

 

Packet A 60 bytes

Packet B

Fragment 1

512 bytes

Packet B

Fragment 2

502 bytes

Packet B

Fragment 3

500 bytes

Packet C

1514 bytes

SPRUEQ6–December 2007

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

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Texas Instruments TMS320DM646x manual Basic Descriptor Description, Typical Descriptor Linked List
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TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

At the core of the TMS320DM646x is the versatile DSP architecture, which optimizes performance for digital signal processing tasks. This architecture allows for real-time processing, enabling the devices to handle complex algorithms necessary for image and video compression, thereby meeting the rigorous demands of modern multimedia applications.

One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

The series supports a wide range of video formats and technologies, including HD video encoding and decoding, which accommodates HD resolution content essential for today’s multimedia applications. Furthermore, the TMS320DM646x integrates hardware accelerators for video compression standards such as H.264 and MPEG-4, which significantly reduce the processing burden on the CPU, resulting in lower power consumption and higher efficiency.

Networking capabilities are another significant feature of the TMS320DM646x. With support for Ethernet, the device can handle streaming media applications and connectivity, facilitating the transmission of high-quality audio and video over the internet. This connectivity is crucial for developing robust IPTV and streaming solutions.

Power management is a primary focus in the design of the TMS320DM646x series. The processors are built to operate efficiently with minimal power consumption, making them suitable for portable and battery-operated devices. The low power characteristics do not compromise performance, enabling high computational capabilities while maintaining energy efficiency.

Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.
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